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Tiled Multicore Processors

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Abstract

For the last few decades Moore’s Law has continually provided exponential growth in the number of transistors on a single chip. This chapter describes a class of architectures, calledtiled multicore architectures, that are designed to exploit massive quantities of on-chip resources in an efficient, scalable manner. Tiled multicore architectures combine each processor core with a switch to create a modular element called a tile. Tiles are replicated on a chip as needed to create multicores with any number of tiles. The Raw processor, a pioneering example of a tiled multicore processor, is examined in detail to explain the philosophy, design, and strengths of such architectures. Raw addresses the challenge of building a general-purpose architecture that performs well on a larger class of stream and embedded computing applications than existing microprocessors, while still running existing ILP-based sequential programs with reasonable performance. Central to achieving this goal is Raw’s ability to exploit all forms of parallelism, including ILP, DLP, TLP, and Stream parallelism. Raw approaches this challenge by implementing plenty of on-chip resources – including logic, wires, and pins – in a tiled arrangement, andexposing them through a new ISA, so that the software can take advantage of these resources for parallel applications. Compared to a traditional superscalar processor, Raw performs within a factor of 2x for sequential applications with a very low degree of ILP, about 2x–9x better for higher levels of ILP, and 10x–100x better when highly parallel applications are coded in a stream language or optimized by hand.

Based on “Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams”, by M.B. Taylor, W. Lee, J.E. Miller, et al. which appeared in The 31st Annual International Symposium on Computer Architecture (ISCA). © 2004 IEEE. [46]

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Acknowledgments

We thank our StreamIt collaborators, specifically M. Gordon, J. Lin, and B. Thies for the StreamIt backend and the corresponding section of this chapter. We are grateful to our collaborators from ISI East including C. Chen, S. Crago, M. French, L. Wang and J. Suh for developing the Raw motherboard, firmware components, and several applications. T. Konstantakopoulos, L. Jakab, F. Ghodrat, M. Seneski, A. Saraswat, R. Barua, A. Ma, J. Babb, M. Stephenson, S. Larsen, V. Sarkar, and several others too numerous to list also contributed to the success of Raw. The Raw chip was fabricated in cooperation with IBM. Raw is funded by DARPA, NSF, ITRI, and the Oxygen Alliance.

Author information

Authors and Affiliations

  1. University of California, San Diego, CA, USA

    Michael B. Taylor

  2. Tilera Corporation, Westborough, MA, USA

    Walter Lee & Ian Bratt

  3. MIT CSAIL, Cambridge, MA, USA

    Jason E. Miller, David Wentzlaff, Henry Hoffmann, Paul R. Johnson, Jason S. Kim, James Psota, Saman Amarasinghe & Anant Agarwal

  4. Veracode, Burlington, MA, USA

    Ben Greenwald

  5. Swasth Foundation, Bangalore, India

    Arvind Saraf

  6. The MITRE Corporation, Bedford, MA, USA

    Nathan Shnidman

  7. IBM Austin Research Laboratory, Austin, TX, USA

    Volker Strumpen

  8. University of Illinois at Urbana - Champaign, Urbana, IL, USA

    Matthew I. Frank

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Editor information

Editors and Affiliations

  1. College of Natural Sciences, University of Texas, Austin, University Station 1, Austin, 78712-0233, U.S.A.

    Stephen W. Keckler

  2. Dept. Electrical Engineering, Stanford University, Stanford, 94305-9510, U.S.A.

    Kunle Olukotun

  3. IBM Software Group, Burnet Rd. 11501, Austin, 78758, U.S.A.

    H. Peter Hofstee

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Taylor, M.B.et al. (2009). Tiled Multicore Processors. In: Keckler, S., Olukotun, K., Hofstee, H. (eds) Multicore Processors and Systems. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0263-4_1

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