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High Speed Hardware Computation of Co-evolution Models

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Part of the book series:Lecture Notes in Computer Science ((LNAI,volume 1674))

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Abstract

Field Programmable Gate Arrays (FPGAs) can provide the most suitable circuits for given problems by reconfiguring its circuits. In this paper, we show that a FPGA chip can achieve about 120 times of speedup compared with a workstation (Ultra-Sparc 200 MHz) in the computation of a co-evolution of strategies and scores in Iterated Prisoner’s Dilemma game. This speedup makes it possible to challenge more complex problems beyond the limitation by software.

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Author information

Authors and Affiliations

  1. Institute of Engineering Mechanics and Systems, University of Tsukuba, 1-1-1 Ten-ou-dai Tsukuba, Ibaraki, 305, Japan

    Yoshiki Yamaguchi, Tsutomu Maruyama & Tsutomu Hoshino

Authors
  1. Yoshiki Yamaguchi

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  2. Tsutomu Maruyama

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  3. Tsutomu Hoshino

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Editor information

Editors and Affiliations

  1. Laboratory of Microprocessors and Interfaces (LAMI) Department of Computer Science, Swiss Federal Institute of Technology (EPFL), CH-1015, Lausanne, Switzerland

    Dario Floreano , Jean-Daniel Nicoud  & Francesco Mondada ,  & 

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© 1999 Springer-Verlag Berlin Heidelberg

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Yamaguchi, Y., Maruyama, T., Hoshino, T. (1999). High Speed Hardware Computation of Co-evolution Models. In: Floreano, D., Nicoud, JD., Mondada, F. (eds) Advances in Artificial Life. ECAL 1999. Lecture Notes in Computer Science(), vol 1674. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48304-7_76

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