Part of the book series:Lecture Notes in Computer Science ((LNTCS,volume 4186))
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Abstract
The Data-Driven Multithreading Chip Multiprocessor (DDM-CMP) architecture has been shown to overcome the power and memory wall limitations by combining two key technologies: the use of the Data-Driven Multithreading (DDM) model of execution, and the Chip-Multiprocessor architecture. DDM is able to hide memory and synchronization latencies providing significant performance gains whereas the use of of the CMP architecture offers high-degree of parallelism at low complexity design and is therefore power efficient.
This paper presents the hardware budget analysis and the runtime support system for the DDM-CMP architecture. The hardware analysis shows that the DDM benefits may be achieved with only a 17% hardware cost increase compared to a traditional chip-multiprocessor implementation. The support for the runtime system was designed in such a way that allows the DDM applications to execute on the DDM-CMP chip using a regular, non-modified, Operating System and CPU cores.
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Authors and Affiliations
Department of Computer Science, University of Cyprus, 75 Kallipoleos Ave., P.O. Box 20537, 1678, Nicosia, Cyprus
Kyriakos Stavrou, Pedro Trancoso & Paraskevas Evripidou
- Kyriakos Stavrou
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- Pedro Trancoso
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- Paraskevas Evripidou
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Computer Systems Architecture Group, University of Amsterdam, The Netherlands
Chris Jesshope
School of Computer Science, University of Hertfordshire, College Lane, AL10 9AB, Hatfield, UK
Colin Egan
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Stavrou, K., Trancoso, P., Evripidou, P. (2006). Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor. In: Jesshope, C., Egan, C. (eds) Advances in Computer Systems Architecture. ACSAC 2006. Lecture Notes in Computer Science, vol 4186. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11859802_20
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