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Abstract
Introduction of sub-90nm technology has made a profound impact on circuit designs. Thus, it requires understanding of existing design styles for desired energy-efficiency. We compare adder designs in the energy-delay space, implemented with Limited Switch Dynamic Logic (LSDL) and Compound Domino Logic (CD) in a 65nm SOI technology. Evaluation results show that LSDL can provide more than 35% energy savings than CD with 25% switching activity at relaxed cycle times greater than 10.5 FO4.
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Authors and Affiliations
IBM Poughkeepsie, 2455 South Rd, Poughkeepsie, NY, 12601, USA
Xiao Yan Yu
IBM T.J. Watson Research Center, 1101 Kitchawan Rd, Route 134, Yorktown Heights, NY, 10598, USA
Robert Montoye
IBM Austin Research Laboratory, 11501 Burnet Rd, Austin, TX, 78758, USA
Kevin Nowka
ACSEL Laboratory, University of California, Davis, CA, 95616, USA
Xiao Yan Yu, Bart Zeydel & Vojin Oklobdzija
- Xiao Yan Yu
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- Robert Montoye
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- Kevin Nowka
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- Bart Zeydel
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- Vojin Oklobdzija
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IMEC, Kapeldreef 75, 3001, Heverlee, Belgium
Johan Vounckx
LIRMM, UMR CNRS/Université de Montpellier II, (C5506), 161 rue Ada, 34392, Montpellier, France
Nadine Azemard
University of Montpellier / LIRMM, II, 161 rue Ada, 34392, Montpellier, France
Philippe Maurine
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Yu, X.Y., Montoye, R., Nowka, K., Zeydel, B., Oklobdzija, V. (2006). Circuit Design Style for Energy Efficiency: LSDL and Compound Domino. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_5
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