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A Very Compact S-Box for AES

  • Conference paper

Part of the book series:Lecture Notes in Computer Science ((LNSC,volume 3659))

Abstract

A key step in the Advanced Encryption Standard (AES) algorithm is the “S-box.” Many implementations of AES have been proposed, for various goals, that effect the S-box in various ways. In particular, the most compact implementations to date of Satoh et al.[14] and Mentens et al.[6] perform the 8-bit Galois field inversion of the S-box using subfields of 4 bits and of 2 bits. Our work refines this approach to achieve a more compact S-box. We examined many choices of basis for each subfield, not only polynomial bases as in previous work, but also normal bases, giving 432 cases. The isomorphism bit matrices are fully optimized, improving on the “greedy algorithm.” Introducing some NOR gates gives further savings. The best case improves on [14] by 20%. This decreased size could help for area-limited hardware implementations, e.g., smart cards, and to allow more copies of the S-box for parallelism and/or pipelining of AES.

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Author information

Authors and Affiliations

  1. Naval Postgraduate School, Monterey, CA, 93943, USA

    D. Canright

Authors
  1. D. Canright

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Editor information

Editors and Affiliations

  1. IBM Watson Research Center, P.O. Box 704, NY 10598, Yorktown Heights, USA

    Josyula R. Rao

  2. Cryptography & Information Security Laboratory, WPI, Worcester, MA, USA

    Berk Sunar

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© 2005 Springer-Verlag Berlin Heidelberg

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Canright, D. (2005). A Very Compact S-Box for AES. In: Rao, J.R., Sunar, B. (eds) Cryptographic Hardware and Embedded Systems – CHES 2005. CHES 2005. Lecture Notes in Computer Science, vol 3659. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11545262_32

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