Movatterモバイル変換

[0]ホーム
URL:

Skip to main content

Advertisement

Springer Nature Link
Log in

The “Backend Duplication” Method

A Leakage-Proof Place-and-Route Strategy for ASICs

  • Conference paper

Part of the book series:Lecture Notes in Computer Science ((LNSC,volume 3659))

Abstract

Several types of logic gates suitable for leakage-proof computations have been put forward[1,2,3,4]. This paper describes a method, called “backend duplication” to assemble secured gates into leakage-proof cryptoprocessors. To the authors’ knowledge, this article is the first CAD-oriented publication to address all the aspects involved in the backend design of secured hardware. The “backend duplication” method achieves the place-and-route of differential netlists. It allows for 100 % placement density and for balanced routing of dual-rail signals. Wires of every other metal layer are free to make turns. In addition, the method does not require any modification to the design rules passed to the router. The “backend duplication” method has been implemented in 0.13μm ASIC technology and successfully tested on various ciphers. The example of the design of a DES module resistant against side-channel attacks is described into details.

Similar content being viewed by others

Keywords

References

  1. Tiri, K., Akmal, M., Verbauwhede, I.: A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards. In: Proceedings of ESSCIRC 2002, pp. 403–406 (2002)

    Google Scholar 

  2. Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In: Proceedings of DATE 2004, pp. 246–251 (2004)

    Google Scholar 

  3. Moore, S., Anderson, R., Cunningham, P., Mullins, R., Taylor, G.: Improving Smart Card Security using Self-timed Circuits. In: Proceedings of ASYNC 2002, pp. 211–218 (2002)

    Google Scholar 

  4. Guilley, S., Hoogvorst, P., Mathieu, Y., Pacalet, R., Provost, J.: CMOS Structures Suitable for Secured Hardware. In: Proceedings of DATE 2004, pp. 1414–1415 (2004)

    Google Scholar 

  5. Kocher, P., Jaffe, J., Jun, B.: Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems. In: Koblitz, N. (ed.) CRYPTO 1996. LNCS, vol. 1109, pp. 104–113. Springer, Heidelberg (1996)

    Google Scholar 

  6. Kocher, P., Jaffe, J., Jun, B.: Differential Power Analysis: Leaking Secrets. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)

    Google Scholar 

  7. Gandolfi, K., Mourtel, C., Olivier, F.: Electromagnetic Analysis: Concrete Results. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 251–261. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  8. Sokolov, D., Murphy, J., Bystrov, A.: Improving the Security of Dual-Rail Circuits. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 282–297. Springer, Heidelberg (2004)

    Chapter  Google Scholar 

  9. Tiri, K., Verbauwhede, I.: Place and Route for Secure Standard Cell Design. In: Proceedings of CARDIS 2004, pp. 143–158 (2004)

    Google Scholar 

  10. Goubin, L., Patarin, J.: DES and Differential Power Analysis (The ”Duplication” Method). In: Koç, Ç.K., Paar, C. (eds.) CHES 1999. LNCS, vol. 1717, pp. 158–172. Springer, Heidelberg (1999)

    Chapter  Google Scholar 

  11. LEF/DEF parsers:http://openeda.si2.org/projects/lefdef/ orhttp://www.cadence.com/partners/languages/languages.aspx

  12. Tiri, K., Verbauwhede, I.: Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 125–136. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  13. Bouesse, G., Renaudin, M., Robisson, B., Beigné, E., Liardet, P.Y., Prevosto, S., Sonzogni, J.: DPA on Quasi Delay Insensitive Asynchronous Circuits: Concrete Results. In: Proceedings of DCIS 2004., Bordeaux, France (2004)

    Google Scholar 

  14. Bouesse, G., Renaudin, M., Dumont, S., Germain, F.: DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. In: Proceedings of DATE 2005, Munich, Germany, pp. 424–429 (2005)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Département communication et électronique, GET/Télécom Paris, CNRS LTCI, 46 rue Barrault, 75634 Cedex 13, Paris, France

    Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu & Renaud Pacalet

Authors
  1. Sylvain Guilley

    You can also search for this author inPubMed Google Scholar

  2. Philippe Hoogvorst

    You can also search for this author inPubMed Google Scholar

  3. Yves Mathieu

    You can also search for this author inPubMed Google Scholar

  4. Renaud Pacalet

    You can also search for this author inPubMed Google Scholar

Editor information

Editors and Affiliations

  1. IBM Watson Research Center, P.O. Box 704, NY 10598, Yorktown Heights, USA

    Josyula R. Rao

  2. Cryptography & Information Security Laboratory, WPI, Worcester, MA, USA

    Berk Sunar

Rights and permissions

Copyright information

© 2005 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Guilley, S., Hoogvorst, P., Mathieu, Y., Pacalet, R. (2005). The “Backend Duplication” Method. In: Rao, J.R., Sunar, B. (eds) Cryptographic Hardware and Embedded Systems – CHES 2005. CHES 2005. Lecture Notes in Computer Science, vol 3659. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11545262_28

Download citation

Publish with us

[8]ページ先頭
©2009-2025 Movatter.jp