Part of the book series:IFIP International Federation for Information Processing ((IFIPAICT,volume 153))
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Abstract
CMOS gates consume different amounts of power whether their output has a falling or a rising edge. Therefore the overall power consumption of a CMOS circuit leaks information about the activity of every single gate. This explains why, using differential power analysis (DPA), one can infer the value of specific nodes within a chip by monitoring its global power consumption only.
We model the information leakage in the framework used by conventional cryptanalysis. The information an attacker can gain is derived as the autocorrelation of the Hamming weight of the guessed value for the key. This model is validated by an exhaustive electrical simulation.
Our model proves that the DPA signal-to-noise ratio increases when the resistance of the substitution box against linear cryptanalysis increases.
This result shows that the better shielded against linear cryptanalysis a block cipher is, the more vulnerable it is to side-channel attacks such as DPA.
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Authors and Affiliations
Département communication et électronique, GET/Télécom Paris, CNRS LTCI, 46 rue Barrault, 75634, Paris Cedex 13, France
Sylvain Guilley & Philippe Hoogvorst
Département communication et électronique, Institut Eurecom, GET/Télécom Paris, CNRS LTCI, BP 193, 2229 route des Crêtes, 06904, Sophia-Antipolis Cedex, France
Renaud Pacalet
- Sylvain Guilley
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- Philippe Hoogvorst
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- Renaud Pacalet
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Editors and Affiliations
UCL, Louvain-la-Neuve, Belgium
Jean-Jacques Quisquater
CNAM, Paris, France
Pierre Paradinas
LAAS-CNRS, Toulouse, France
Yves Deswarte & Anas Abou El Kalam &
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Guilley, S., Hoogvorst, P., Pacalet, R. (2004). Differential Power Analysis Model and Some Results. In: Quisquater, JJ., Paradinas, P., Deswarte, Y., El Kalam, A.A. (eds) Smart Card Research and Advanced Applications VI. IFIP International Federation for Information Processing, vol 153. Springer, Boston, MA. https://doi.org/10.1007/1-4020-8147-2_9
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