Movatterモバイル変換

• nvJPEG
  • NVJPEG_BACKEND_GPU_HYBRID has an issue when handling bit-streams which have corruption in the scan.

• cuFFT now accepts __nv_bfloat16 input and output data type for power-of-two sizes with single precision computations within the kernels.

• Note that starting with CUDA 11.0, the minimum recommended GCC compiler is at least GCC 5 due to C++11 requirements in CUDA libraries e.g. cuFFT and CUB. On distributions such as RHEL 7 or CentOS 7 that may use an older GCC toolchain by default, it is recommended to use a newer GCC toolchain with CUDA 11.0. Newer GCC toolchains are available with the Red Hat Developer Toolset.
• cublasGemmStridedBatchedEx() andcublasLtMatmul() may cause misaligned memory access errors in rare cases, whenAtype orCtype isCUDA_R_16F orCUDA_R_16BF andstrideA,strideB orstrideC are not multiple of 8 and internal heuristics determines to use certain Tensor Core enabled kernels. A suggested work around is to specify CUBLASLT_MATMUL_PREF_MIN_ALIGNMENT_<A,B,C,D>_BYTES accordingly to matrix stride used when callingcublasLtMatmulAlgoGetHeuristic().

• cusparse<t>gemmi()
• cusparseXaxpyi,cusparseXgthr,cusparseXgthrz,cusparseXroti,cusparseXsctr

• The following new compilers are supported as host compilers for the CUDA compiler (nvcc)

  • Clang 9
  • GCC 9
  • PGI 20.1
  • ICC 19.1
  • Arm C/C++ 19.2
• The default compilation target for nvcc is nowsm_52. Other older targets are either deprecated or no longer supported. See the Deprecated Features section for more details.
• Added support for Link-Time Optimization (LTO). LTO enables cross-file inlining and optimization when doing separate compilation. To use LTO, add-dlto to both the compile and link commands, for example "nvcc -arch=sm_70 -dlto a.cu b.cu". LTO is currently in technical preview. See the section titled "Optimization of Separate Compilation" in the nvcc manual for more information.

• nvcc added two new flags ('-Wdefault-stream-launch') and ('-Werror=default-stream-launch') to generate a warning and an error, respectively, when a stream argument is not explicitly specified in the<<<...>>> kernel launch syntax. For example:

  $ cat j1.cu

  __global__ void foo() { }

  int main() { foo<<<1,1>>>();

  }

  $nvcc -Wdefault-stream-launch j1.cu -ptx

  j1.cu(2): warning: explicit stream argument not provided in kernel launch

  $nvcc -Werror=default-stream-launch j1.cu -c

  j1.cu(2): error: explicit stream argument not provided in kernel launch

• The compiler optimizer now implements more aggressive dead code elimination for__shared__ variables whose value is not used. For example:

  //--__device__ void foo() {

  __shared__ int xxx;

  xxx = 1;

  }

  In previous CUDA toolkits, the variable "xxx" is still present in the generated PTX. With CUDA 11 or later, the variable may be removed in the generated PTX, because its value is not used. Marking the variable as "volatile" will inhibit this compiler optimization.

• In previous CUDA toolkits, NVRTC on Linux incorrectly added "/usr/include" to the default header file search path. This issue has been fixed; NVRTC in CUDA 11.0 and later will not implicitly add '/usr/include' to the header file search path.

  If some included files are present inside/usr/include, the NVRTCnvrtcCompileProgram() API call must now be explicitly passed the "/usr/include" path with the "-I" flag.

• nvcc now allows options that take a single argument to be redefined. If the redefinition is incompatible with the earlier instance, a warning is issued. For example:

  // the following command line is now accepted, previously nvcc gave an error

  $nvcc -rdc=true -rdc=true -c j1.cu

  // the following command line is now accepted with a warning (due to incompatible redefinition of '-rdc' argument), previously nvcc gave an error

  $nvcc -rdc=true -rdc=false -c j1.cu

  nvcc warning : incompatible redefinition for option 'relocatable-device-code'

• nvcc implements a new flag '-extra-device-vectorization' , which enables more aggressive vectorization of device code.
• Added support for C++17. Note that C++17 support is a technical preview feature for CUDA 11.0.
• Added support for__attribute__((visibility("default"))).

• The following developer tools are supported for remote (target) debugging/profiling of applications on macOS hosts:
  • Nsight Compute
  • Nsight Systems
  • cuda-gdb
  • NVVP
• For new features, improvements, and bug fixes in CUPTI, see the changelog.
• For new features, improvements, and bug fixes in Nsight Compute, see thechangelog.
• Cuda-gdb is now upgraded to support GDB 8.2.
• A new tool called Compute Sanitizer, for memory and race condition checking, is now included as part of CUDA 11.0.

• CUDA Math libraries toolchain uses C++11 features, and a C++11-compatible standard library is required on the host.
• cuBLAS 11.0.0
• cuFFT 10.1.3
• cuRAND 10.2.0
• cuSPARSE 11.0.0
• cuSOLVER 10.4.0
• NPP 11.0.0
• nvJPEG 11.0.0

• cuBLASLt Matrix Multiplication adds support for fused ReLU and bias operations for all floating point types except double precision (FP64).
• Improved batched TRSM performance for matrices larger than 256.
• Many performance improvements have been implemented for the NVIDIA Ampere, Volta, and Turing Architecture based GPUs.
• With this release, on Linux systems, the cuBLAS libraries listed below are now installed in the/usr/local/cuda-11.0 (./lib64/ for lib and./include/ for headers) directories as shared and static libraries.
• ThecuBLASLt logging mechanism can be enabled by setting the following environment variables before launching the target application:
  • CUBLASLT_LOG_LEVEL=<level> - while level is one of the following levels:
    • "0" - Off - logging is disabled (default)
    • "1" - Error - only errors will be logged
    • "2" - Trace - API calls will be logged with their parameters and important information
  • CUBLASLT_LOG_FILE=<value> - while value is a file name in the format of "<file_name>.%i", %i will be replaced with the process id. If CUBLASLT_LOG_FILE is not defined, the log messages are printed to stdout.
• For matrix multiplication APIs:
  • cublasGemmEx,cublasGemmBatchedEx,cublasGemmStridedBatchedEx andcublasLtMatmul has new data type support for BFLOAT16 (CUDA_R_16BF).
  • The newly introducedcomputeType_t changes function prototypes on the API:cublasGemmEx,cublasGemmBatchedEx, andcublasGemmStridedBatchedEx have a new signature that usescublasComputeType_t for thecomputeType parameter. Backward compatibility is ensured with internal mapping for C users and with added overload for C++ users.
  • cublasLtMatmulDescCreate,cublasLtMatmulAlgoGetIds, andcublasLtMatmulAlgoInit have new signatures that usecublasComputeType_t.
  • A new compute type TensorFloat32 (TF32) has been added to provide tensor core acceleration for FP32 matrix multiplication routines with full dynamic range and increased precision compared to BFLOAT16.
  • New compute modes Default, Pedantic, and Fast have been introduced to offer more control over compute precision used.
  • *Init versions of*Create functions are introduced in cublasLt to allow for simple wrappers that hold all descriptors on stack.
  • Experimental feature of cuBLASLt API logging is introduced.
  • Tensor cores are now enabled by default for half-, and mixed-precision- matrix multiplications.
  • Double precision tensor cores (DMMA) are used automatically.
  • Tensor cores can now be used for all sizes and data alignments and for all GPU architectures:
    • Selection of these kernels through cuBLAS heuristics is automatic and will depend on factors such as math mode setting as well as whether it will run faster than the non-tensor core kernels.
    • Users should note that while these new kernels that use tensor cores for all unaligned cases are expected to perform faster than non-tensor core based kernels but slower than kernels that can be run when all buffers are well aligned.

• cuFFT now accepts __nv_bfloat16 input and output data type for power-of-two sizes with single precision computations within the kernels.
• Reoptimized power of 2 FFT kernels on Volta and Turing architectures.

• Added new Generic APIs for Axpby (cusparseAxpby), Scatter (cusparseScatter), Gather (cusparseGather), Givens rotation (cusparseRot). __nv_bfloat16/ __nv_bfloat162 data types and 64-bit indices are also supported.

• This release adds the following features for cusparseSpMM:

  • Support for row-major layout for cusparseSpMM for both CSR and COO format
  • Support for 64-bit indices
  • Support for __nv_bfloat16 and __nv_bfloat162 data types
  • Support for the following stridedbatch mode:

    • Ci=A⋅Bi

    • Ci=Ai⋅B

    • Ci=Ai⋅Bi

• Added new generic APIs and improved performance for sparse matrix-sparse matrix multiplication (SpGEMM):cusparseSpGEMM_workEstimation,cusparseSpGEMM_compute, andcusparseSpGEMM_copy.
• SpVV: added support for__nv_bfloat16.

• Add 64-bit API of GESVD. The new routine cusolverDnGesvd_bufferSize() fills the missing parameters in 32-bit API cusolverDn[S|D|C|Z]gesvd_bufferSize() such that it can estimate the size of the workspace accurately.
• Added the single process multi-GPU Cholesky factorization capabilities POTRF, POTRS and POTRI in cusolverMG library.
• Added 64-bit APIs forgetrf,getrs,potrf,potrs,geqrf,syevd andsyevdx.

• This release adds more control and helpful functionalities for the Tensor Cores Accelerated Iterative Refinement Solver TCAIRS.

  • In addition to the previously released TCAIRS-LU based solver a new TCAIRS-QR based solver for real and complex systems with one or multiple right hand sides is introduced.
  • In addition to the FP64, FP32 and FP16 computational precisions two new computational precisions types are supported: the BFLOAT16 and the TensorFloat32 (TF32). Both TCAIRS-LU and TCAIRS-QR come with the five computational precisions options. Tensor Float (TF32), introduced with NVIDIA Ampere Architecture GPUs, is the most robust tensor core accelerated compute mode for the iterative refinement solver. It is able to solve the widest range of problems in HPC arising from different applications and provides up to 4X and 5X speedup for real and complex systems, respectively. On Volta and Turing architecture GPUs, half precision tensor core acceleration is recommended. In cases where the iterative refinement solver fails to converge to the desired accuracy (double precision in most cases), it is recommended to use full double precision factorization and solve (such as [D,Z]GETRF and [D,Z]GETRS or cusolverDn[DD,ZZ]gesv).
  • TCAIRS (LU and QR) are released with easy LAPACK-style APIs (drop-in replacement) as well as expert generic APIs that give users a lot of control of the internal of the solver. These support all five computational precisions.
  • Simple and Expert APIs now support all five computational precisions.
  • Expert TCAIRS solvers APIs allow users to choose between 4 methods of refinement.
  • Expert TCAIRS solvers APIs now support a no-refinement option which means they behave as standard Xgesv/Xgels solvers without refinement.
• Performance improvements of the TCAIRS solver for NVIDIA Ampere, Volta, and Turing Architecture based GPUs.

• Batched Image Label Markers Compression that removes sparseness between marker label IDs output from LabelMarkers call.
• Image Flood Fill functionality fills a connected region of an image with a specified new value.
• Added batching support for nppiLabelMarkersUF functions.
• Added thenppiCompressMarkerLabelsUF_32u_C1IR function.

• AddednppiSegmentWatershed functions.

• Added sample apps on GitHub demonstrating the use of NPP application managed stream contexts along with watershed segmentation and batched and compressed UF image label markers functions.
• Added support for non-blocking streams.

• Add arithmetic support for__nv_bfloat16 floating-point data type with 8 bits of exponent, 7 explicit bits of mantissa.
• Performance and accuracy improvements in single precision math functions:fmodf,expf,exp10f,sinhf, andcoshf.

General CUDA

• Support for Red Hat Enterprise Linux (RHEL) and CentOS 6.x is dropped.
• Support for Keplersm_30 andsm_32 architecture based products is dropped.

• Support for the following compute capabilities are deprecated in the CUDA Toolkit:

  • sm_35 (Kepler)

  • sm_37 (Kepler)

  • sm_50 (Maxwell)

  For more information on GPU products and compute capability, seehttps://developer.nvidia.com/cuda-gpus.

• Support for Linux cluster packages is dropped.
• CUDA 11.0 does not support macOS for developing and running CUDA applications. Note that some of the CUDA developer tools are still supported on macOS hosts for remote (target) debugging and profiling. See the CUDA Tools section for more information.

• CUDA 11.0 no longer supports development of CUDA applications on the following Windows distributions:

  • Windows 7
  • Windows 8
  • Windows Server 2012 R2
• nvGraph is no longer included as part of the CUDA Toolkit installers. See thecuGraph project as part of RAPIDS; the project includes algorithms from nvGraph and more.
• The context creation flag CU_CTX_MAP_HOST (to support mapped pinned allocations) is deprecated and will be removed in a future release of CUDA.

CUDA Developer Tools

• Nsight Eclipse Edition standalone is dropped in CUDA 11.0.
• Nsight Compute does not support profiling on Pascal architectures.
• Nsight VSE, Nsight EE Plugin, cuda-gdb, nvprof, Visual Profiler, and memcheck are reducing support for the following architectures:
  • Support for Keplersm_30 andsm_32 architecture based products (deprecated since CUDA 10.2) has beeen dropped.
  • Support for the following compute capabilities (deprecated since CUDA 10.2) will be dropped in an upcoming CUDA release:
    • sm_35 (Kepler)
    • sm_37 (Kepler)
    • sm_50 (Maxwell)

CUDA Libraries - cuBLAS

• Algorithm selection incublasGemmEx APIs (including batched variants) is non-functional for NVIDIA Ampere Architecture GPUs. Regardless of selection it will default to a heuristics selection. Users are encouraged to use thecublasLt APIs for algorithm selection functionality.
• The matrix multiply math modeCUBLAS_TENSOR_OP_MATH is being deprecated and will be removed in a future release. Users are encouraged to use the newcublasComputeType_t enumeration to define compute precision.

CUDA Libraries -- cuSOLVER

• TCAIRS-LU expertcusolverDnIRSXgesv() and some of its configuration functions undergo a minor API change.

CUDA Libraries -- cuSPARSE

The following functions have been removed:

• cusparse<t>gemmi()
• cusparseXaxpyi,cusparseXgthr,cusparseXgthrz,cusparseXroti,cusparseXsctr
• Hybrid format enums and helper functions:cusparseHybPartition_t,cusparseHybPartition_t,cusparseCreateHybMat,cusparseDestroyHybMat
• Triangular solver enums and helper functions:cusparseSolveAnalysisInfo_t,cusparseCreateSolveAnalysisInfo,cusparseDestroySolveAnalysisInfo
• Sparse dot product:cusparseXdoti,cusparseXdotci
• Sparse matrix-vector multiplication:cusparseXcsrmv,cusparseXcsrmv_mp
• Sparse matrix-matrix multiplication:cusparseXcsrmm,cusparseXcsrmm2
• Sparse triangular-single vector solver:cusparseXcsrsv_analysis,cusparseCsrsv_analysisEx,cusparseXcsrsv_solve,cusparseCsrsv_solveEx
• Sparse triangular-multiple vectors solver:cusparseXcsrsm_analysis,cusparseXcsrsm_solve
• Sparse hybrid format solver:cusparseXhybsv_analysis,cusparseShybsv_solve
• Extra functions:cusparseXcsrgeamNnz,cusparseScsrgeam,cusparseXcsrgemmNnz,cusparseXcsrgemm
• Incomplete Cholesky Factorization, level 0:cusparseXcsric0
• Incomplete LU Factorization, level 0:cusparseXcsrilu0,cusparseCsrilu0Ex
• Tridiagonal Solver:cusparseXgtsv,cusparseXgtsv_nopivot
• Batched Tridiagonal Solver:cusparseXgtsvStridedBatch
• Reordering:cusparseXcsc2hyb,cusparseXcsr2hyb,cusparseXdense2hyb,cusparseXhyb2csc,cusparseXhyb2csr,cusparseXhyb2dense

The following functions have been deprecated:

• SpGEMM:cusparseXcsrgemm2_bufferSizeExt,cusparseXcsrgemm2Nnz,cusparseXcsrgemm2

CUDA Libraries -- nvJPEG

• The following multiphase APIs have been removed:

  • nvjpegStatus_t NVJPEGAPI nvjpegDecodePhaseOne

  • nvjpegStatus_t NVJPEGAPI nvjpegDecodePhaseTwo

  • nvjpegStatus_t NVJPEGAPI nvjpegDecodePhaseThree

  • nvjpegStatus_t NVJPEGAPI nvjpegDecodeBatchedPhaseOne

  • nvjpegStatus_t NVJPEGAPI nvjpegDecodeBatchedPhaseTwo

• Fixed an issue where GPU passthrough on arm64 systems was not functional. GPU passthrough is now supported on arm64, but there may be a small performance impact to workloads (compared to bare-metal) on some system configurations.
• Fixed an issue where starting X on systems with arm64 CPUs and NVIDIA GPUs would result in a crash.

• Fixed an issue where NVCC throws a compilation error when a value > 32768 was used in an__attribute__((aligned(value))).
• Fixed an issue in PTXAS where a 64-bit integer modulo operation resulted in illegal memory access.
• Fixed an issue with NVCC where code using the__is_implicitly_default_constructible type trait would result in an access violation.
• Fixed an issue where NVRTC (nvrtcCompileProgram()) would enter into infinite loops triggered by some code patterns.
• Fixed implementation ofnvrtcGetTypeName() on Windows to callUnDecorateSymbolName() with the correct flags. The string returned byUnDecorateSymbolName() may contain Microsoft specific keywords '__cdecl' and '__ptr64'. NVRTC has been updated to define these symbols to empty during compilation. This allows use of names returned bynvrtcGetTypeName() to be directly used innvrtcAddNameExpression/nvrtcGetLoweredName().
• Fixed a compilation time issue in NVCC to improve handling of large numbers of explicit specialization of function templates.

• Reduced R2C/C2R plan memory usage to previous levels.
• Resolved bug introduced in 10.1 update 1 that caused incorrect results when using custom strides, batched 2D plans and certain sizes on Volta and later.

• Introduced CURAND_ORDERING_PSEUDO_LEGACY ordering. Starting with CUDA 10.0, the ordering of random numbers returned by MTGP32 and MRG32k3a generators are no longer the same as previous releases despite being guaranteed by the documentation for the CURAND_ORDERING_PSEUDO_DEFAULT setting. The CURAND_ORDERING_PSEUDO_LEGACY provides pre-CUDA 10.0 ordering for MTGP32 and MRG32k3a generators.
• Starting with CUDA 11.0 CURAND_ORDERING_PSEUDO_DEFAULT is the same as CURAND_ORDERING_PSEUDO_BEST for all generators except MT19937. Only CURAND_ORDERING_PSEUDO_LEGACY is guaranteed to provide the same for all future cuRAND releases.

• Fixed an issue where SYEVD/SYGVD would fail and return error code 7 if the matrix is zero and the dimension is bigger than 25.
• Fixed a race condition of GETRF when running with other kernels concurrently.
• Fixed the pivoting strategy of [c|z]getrf to be compliant with LAPACK.
• Fixed NAN and INF values that might result in the TCAIRS-LU solver when FP16 was used and matrix entries are outside FP16 range.
• Fixed the pivoting strategy of [c|z]getrf to be compliant with LAPACK.
• Previously,cusolverSpDcsrlsvchol could overflow 32-bit signed integer when zero fill-in is huge. Such overflow causes memory corruption.cusolverSpDcsrlsvchol now returnsCUSOLVER_STATUS_ALLOC_FAILED when integer overflow happens.

• Corrected documented maximum ulp error thresholds inerfcinvf andpowf.

• Improvedcuda_fp16.h interoperability with Visual Studio C++ compiler.
• Updated libdevice user guide and CUDA math API definitions forj1,j1f,fmod,fmodf,ilogb, andilogbf math functions.

• Stability and performance fixes to Image Label Markers and Image Label Markers Compression.
• Improved quality ofnppiLabelMarkersUF functions.
• nppiCompressMarkerLabelsUF_32u_C1IR can now handle a huge number of labels generated by the nppiLabelMarkersUF function.

• ThecuptiFinalize() API now allows on-demand detachability of the profiling tool.

• The nanosleep PTX instruction for Volta and Turing is not supported in this release of CUDA. It may be fully supported in a future releaseof CUDA. There may be references to nanosleep in the compiler headers (such asinclude/crt/sm_70_rt*). Developers are encouraged to not use this instruction in their CUDA applications on Volta and Turing until it is fully supported.
• Read-only memory mappings (viaCU_MEM_ACCESS_FLAGS_PROT_READ inCUmemAccess_flags) withcuMemSetAccess() API will result in an error. Read-only memory mappings are currently not supported and may be added in a future release of CUDA.
• Note that the R450 driver bundled with this release of CUDA 11 does not officially support Windows 10 May 2020 Update and may have issues
• GPU workloads are executed on GPU hardware engines. On Windows, these engines are represented by “nodes”. With Hardware Scheduling disabled for Windows 10 May 2020 Update, some NVIDIA GPU engines are represented by virtual nodes, and multiple virtual nodes may represent more than one GPU hardware engine. This is done to achieve better parallel execution of workloads. Examples of these virtual nodes are “Cuda”, “Compute_0”, “Compute_1”, and “Graphics_1” as shown in Windows Task Manager. These correspond to the same underlying hardware engines as the “3D” node in Windows Task Manager. With Hardware Scheduling enabled, the virtual nodes are no longer needed, and Task Manager shows only the “3D”node for the previous “3D” node and multiple virtual nodes shown before, combined. CUDA is still supported in this scenario.

• The legacy profiling tools nvprof and NVVP do not support the NVIDIA Ampere architecture.
• Arithmetic is not supported on__nv_bfloat16 floating point variables in the Nsight debugger watch window.
• In some cases, cuda-gdb has a dependency on Python that can be resolved by installing the libpython-dev packages on Linux. For example, on Ubuntu use:sudo apt install libpython-dev.
• For remote debugging on macOS with cuda-gdb, disassembly of code is not supported and may return an error. This issue will be addressed in the production release of CUDA 11.0.

• Sample 0_Simple/simpleSeparateCompilation fails to build with the error "cc: unknown target 'gcc_ntox86". The workaround to allow the build to pass is by passing additionallyEXTRA_NVCCFLAGS="-arbin $QNX_HOST/usr/bin/aarch64-unknown-nto-qnx7.0.0-ar".

• cuFFT modifies C2R input buffer for some non-strided FFT plans.
• There is a known issue with certain cuFFT plans that causes an assertion in the execution phase of certain plans. This applies to plans with all of the following characteristics: real input to complex output (R2C), in-place, native compatibility mode, certain even transform sizes, and more than one batch.

• ThenppiCopy API is limited by CUDA thread for large image size. Maximum image limits is a minimum of 16 * 65,535 = 1,048,560 horizontal pixels of any data type and number of channels and 8 * 65,535 = 524,280 vertical pixels for a maximum total of 549,739,036,800 pixels.

Acknowledgments

NVIDIA extends thanks to Professor Mike Giles of Oxford University for providing the initial code for the optimized version of the device implementation of the double-precisionexp() function found in this release of the CUDA toolkit.

NVIDIA acknowledges Scott Gray for his work on small-tile GEMM kernels for Pascal. These kernels were originally developed for OpenAI and included since cuBLAS 8.0.61.2.

Notice

ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS, AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY, "MATERIALS") ARE BEING PROVIDED "AS IS." NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY, OR OTHERWISE WITH RESPECT TO THE MATERIALS, AND EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE.

Information furnished is believed to be accurate and reliable. However, NVIDIA Corporation assumes no responsibility for the consequences of use of such information or for any infringement of patents or other rights of third parties that may result from its use. No license is granted by implication of otherwise under any patent rights of NVIDIA Corporation. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all other information previously supplied. NVIDIA Corporation products are not authorized as critical components in life support devices or systems without express written approval of NVIDIA Corporation.

Trademarks

NVIDIA and the NVIDIA logo are trademarks or registered trademarks of NVIDIA Corporation in the U.S. and other countries. Other company and product names may be trademarks of the respective companies with which they are associated.

Copyright

©2007-2020 NVIDIA Corporation. All rights reserved.

This product includes software developed by the Syncro Soft SRL (http://www.sync.ro/).