When you create a virtual machine (VM) or bare metal instance usingCompute Engine, you specify a machine series and a machine type for theinstance. Each machine series is associated with one or more CPU platforms.If there are multiple CPU platforms available for a machine series, you canselect aminimum CPUplatform for the compute instance.

A CPU platform offers multiple physical processors, and each of these processorsis referred to as a core. For the processors available onCompute Engine, a single CPU core can run as multiple hardware threadsthroughSimultaneous multithreading (SMT),which is known on Intel processors asIntel Hyper-Threading Technology.On Compute Engine, each hardware thread is called a virtual CPU(vCPU). Some machine series don't use SMT, and each vCPU instead represents acore. When vCPUs are reported to the instance as occupying different virtualcores, Compute Engine verifies that these vCPUs never share the samephysical core.

Themachine type of your compute instancespecifies its number of vCPUs, and you can infer its number of physical CPUcores using the default vCPU per core ratio for that machine series:

• For the C4A, N4A (Preview),T2D, T2A, H4D, H3, and A4X machine series,Compute Engine instances always have one vCPU per core.
• For all other machine series, the compute instances have two vCPUs per coreby default.

You can optionallyset the number of threads per core,to a non-default value, which might benefit some workloads. Importantly, whenyou do this, the machine type of your compute instance no longer reflects thecorrect number of vCPUs. Instead, thepricingand number of physical CPU cores remains the same as it would be for thedefault two vCPUs per core ratio, and the number of vCPUs is half of thevalue indicated by the machine type.

Arm processors

For Arm processors, Compute Engine uses one thread per core. Each vCPUmaps to a physical core with no SMT.

The following table describes the Arm processors that are available forCompute Engine instances.

x86 processors

For most x86 processors, each vCPU is implemented as a single hardware thread.

Intel processors

On Intel Xeon processors,Intel Hyper-Threading Technologysupports multiple threads running concurrently on each core. Themachine type of yourcompute instance determines the number of its vCPUs and memory.

The H3 machine series doesn't use hyper-threading, and one vCPUrepresents one physical core.

AMD processors

AMD processors provide optimized performance and scalability using SMT. Inalmost all cases, Compute Engine uses two threads per core, and eachvCPU is one thread. H4D and Tau T2D are the exceptions whereCompute Engine uses one thread per core and each vCPU maps to aphysical core.

Themachine typeof your compute instance determines the number of vCPUs and amount of memoryallocated to the instance.

Frequency behavior

The previous tables describe the hardware specifications of the CPUs that areavailable with Compute Engine, but keep the following points in mind:

• Frequency: A PC's frequency, or clock speed, measures the number ofcycles the CPU executes per second, measured in GHz (gigahertz). Generally,higher frequencies indicate better performance. However, different CPU designshandle instructions differently, so an older CPU with a higher clock speedcan be outperformed by a newer CPU with a lower clock speed because the newerarchitecture deals with instructions more efficiently.

• Base frequency: The frequency at which the CPU runs when the system isidle or under light load. When running at its base frequency, the CPU drawsless power and produces less heat.

  A compute instance's guest environment reflects the base frequency,regardless of what frequency the CPU is actually running at.

• All-core turbo frequency: The frequency at which each CPU typicallyruns when all cores in the socket are not idle at the same time. Differentworkloads place different demands on a system's CPU. Boost technologiesaddress this difference and help processes adapt to the workload demands byincreasing the CPU's frequency.

  • Most compute instances get the all-core turbo frequency, even if onlythe base frequency is advertised to the guest environment.
  • Ampere Altra Arm processors can provide more predictable performancebecause the frequency for Arm processors is always the all-core turbofrequency.

  • C4 instances areable to run at all-core-max turbo frequency by setting theAdvancedMachineFeaturefield toALL_CORE_MAX. If this field is unset, the instance runs atthe default setting, which is unrestricted frequency.

    TheALL_CORE_MAX setting isn't available with C4D or C4A computeinstances.

• Max turbo frequency: The frequency a CPU targets when stressed by ademanding application like a video game or design modeling application. It'sthe maximum single-core frequency that a CPU achieves without overclocking.

• Processor power management technologies: Intel processors support multipletechnologies to optimize the power consumption. These technologies are dividedinto two categories, or states:

  • C-states are states when the CPU has reduced or turned off selectedfunctions.
  • P-states provide a way to scale the frequency and voltage at which theprocessor runs so as to reduce the power consumption of the CPU.

  All C4 machine types, and certain C2 (30, 60 vCPUs), C2D (56, 112 vCPUs) andM2 (208, 416 vCPUs) machine types support instance-provided C-state hints byway of theMWAIT instruction.

  Compute Engine instances don't provide any facilities for customercontrol of P-states.

CPU features

Chip manufacturers add advanced technologies for computations, graphics,virtualization, and memory management to the CPUs they produce. Google Cloudsupports the use of some of these advanced features with Compute Engine.

Advanced Vector Extensions

Advanced Vector Extensions (AVX) are single instruction, multiple data (SIMD)extensions to the x86 instruction set architecture for microprocessors fromIntel and Advanced Micro Devices (AMD). AVX provides new instructions and anew coding scheme.

For more information, seeAdvanced Vector Extensions.

AVX is available with all x86 processors used by Compute Engine.

Advanced Vector Extensions (AVX2)

AVX2 (also known as Haswell New Instructions) introduces the followingadditions to AVX:

• Expands most vector integer SSE and AVX instructions to 256 bits
• Adds support for Gather, enabling vector elements to be loaded fromnon-contiguous memory locations
• Any-to-any permutes with DWORD- and QWORD-granularity
• Vector shifts

AVX2 is available with the following CPU platforms:

• Intel Xeon E5 v3 (Haswell) and newer processors
• All AMD processors

Advanced Vector Extensions (AVX512)

AVX-512 expands AVX to 512-bit support using the EVEX prefix encoding. AVX-512provides built-in acceleration for demanding workloads that involveheavy vector-based processing. The large register for the AVX-512 acceleratorsupports 32 double-precision and 64 single-precision floating-point numbers,in addition to eight 64-bit and 16 32-bit integers.

For more information about AVX-512, seeWhat is Intel AVX-512?.

AVX-512 is available with the following CPU platforms:

• Intel Xeon Scalable Processor (Skylake) 1st Generation and newer processors
• AMD EPYC Genoa 4th Generation and newer processors

Advanced Matrix Extensions

Intel Advanced Matrix Extensions (AMX) is a new instruction set architecture (ISA) extension designed to accelerateartificial intelligence (AI) and machine learning (ML) workloads. AMXintroduces new instructions that can be used to perform matrix multiplicationand convolution operations, which are two of the most common operations in AIand ML.

AMX introduces 2-dimensional registers calledtiles upon which acceleratorscan perform operations. AMX is intended as an extensible architecture. The firstaccelerator implemented is called tile matrix multiply unit (TMUL). EachCPU core of the Sapphire Rapids processor has an independent AMX TMUL unit.

For technical details about Intel AMX, seeIntel AMX support in 5.16.Intel offers a tutorial on AMX atCode Sample: Intel Advanced Matrix Extensions (Intel AMX) - Intrinsics Functions.

AMX is available with Intel Xeon 4th generation (Sapphire Rapids) and laterprocessors. AMX is not available with AMD or Arm processors.

Requirements for using AMX

Intel AMX instructions have certain minimum software requirements such as:

• For custom images, AMX is supported with Linux kernel version 5.16 orlater.
• Compute Engine offers support for AMX in the followingpublic images:
  • CentOS Stream 9
  • Container-Optimized OS 109 LTS or later
  • RHEL 8 (latest build) or later
  • Rocky Linux 8 (latest build) or later
  • Ubuntu 22.04 or later
  • Windows Server 2022 or later
• Tensorflow2.9.1 or greater
• Intel extension forIntel Optimization for PyTorch

CPU features available to bare metal instances

In addition to offering all the raw compute resources of the server, bare metalinstances that run on 4th generation and later Intel Xeon Scalable Processorscan use several on board, function-specific accelerators and offloads:

• Intel-QAT: Intel QuickAssist Technology (Intel QAT) acceleratescompression, encryption, and decryption
• Intel-DLB: Intel Dynamic Load Balancer (Intel DLB) helps to speed updata queues
• Intel IAA: Intel In-Memory Analytics Accelerator (Intel IAA) improvesquery processing performance.
• Intel DSA: Intel Data Streaming Accelerator (Intel DSA) helps tocopy and move data faster.

Confidential Computing

To protect your data while it's in use, CPU platforms that supportConfidential Computing technologies can be used to createConfidential VMinstances.

To learn more about the requirements for creating a Confidential VMinstance, seeSupported configurations.

What's next

• Learn more aboutMachine families.
• Learn more aboutCompute Engine instances.
• Learn more aboutImages.
• Learn how toSpecify a minimum CPU platform.