Library Reference

version 2.112.0

Internal API

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core.cpuid

Identify the characteristics of the host CPU, providing information about cache sizes and assembly optimisation hints. This module is provided primarily for assembly language programmers.

ReferencesSome of this information was extremely difficult to track down. Some of the documents below were found only in cached versions stored by search engines! This code relies on information found in:

"Intel(R) 64 and IA-32 Architectures Software Developers Manual, Volume 2A: Instruction Set Reference, A-M" (2007).
"AMD CPUID Specification", Advanced Micro Devices, Rev 2.28 (2008).
"AMD Processor Recognition Application Note For Processors Prior to AMD Family 0Fh Processors", Advanced Micro Devices, Rev 3.13 (2005).
"AMD Geode(TM) GX Processors Data Book", Advanced Micro Devices, Publication ID 31505E, (2005).
"AMD K6 Processor Code Optimisation", Advanced Micro Devices, Rev D (2000).
"Application note 106: Software Customization for the 6x86 Family", Cyrix Corporation, Rev 1.5 (1998)
http://www.datasheetcatalog.org/datasheet/nationalsemiconductor/GX1.pdf
"Geode(TM) GX1 Processor Series Low Power Integrated X86 Solution", National Semiconductor, (2002)
"The VIA Isaiah Architecture", G. Glenn Henry, Centaur Technology, Inc (2008).
http://www.sandpile.org/ia32/cpuid.htm
http://www.akkadia.org/drepper/cpumemory.pdf
"What every programmer should know about memory", Ulrich Depper, Red Hat, Inc., (2007).
"CPU Identification by the Windows Kernel", G. Chappell (2009).http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm
"Intel(R) Processor Identification and the CPUID Instruction, Application Note 485" (2009).

Bugs:

Currently only works on x86 and Itanium CPUs. Many processors have bugs in their microcode for the CPUID instruction, so sometimes the cache information may be incorrect.

License:

Boost License 1.0

Authors:

Don Clugston, Tomas Lindquist Olsen <tomas@famolsen.dk>

Sourcecore/cpuid.d

structCacheInfo;

Cache size and behaviour

size_tsize;

Size of the cache, in kilobytes, per CPU.For L1 unified (data + code) caches, this size is half the physical size.(we don't halve it for larger sizes, since normallydata size is much greater than code size for critical loops).

ubyteassociativity;

Number of ways of associativity, eg:

1 = direct mapped
2 = 2-way set associative
3 = 3-way set associative
ubyte.max = fully associative

uintlineSize;

Number of bytes read into the cache when a cache miss occurs.

CacheInfo[5]datacache;

Scheduled for deprecation. Please usedataCaches instead.

pure nothrow @nogc @property @trusted const(CacheInfo)[5]dataCaches();

The data caches. If there are fewer than 5 physical caches levels,the remaining levels are set to size_t.max (== entire memory space)

pure nothrow @nogc @property @trusted stringvendor();

Returns vendor string, for display purposes only.Do NOT use this to determine features!Note that some CPUs have programmable vendorIDs.

pure nothrow @nogc @property @trusted stringprocessor();

Returns processor string, for display purposes only

pure nothrow @nogc @property @trusted boolx87onChip();

Does it have an x87 FPU on-chip?

pure nothrow @nogc @property @trusted boolmmx();

Is MMX supported?

pure nothrow @nogc @property @trusted boolsse();

Is SSE supported?

pure nothrow @nogc @property @trusted boolsse2();

Is SSE2 supported?

pure nothrow @nogc @property @trusted boolsse3();

Is SSE3 supported?

pure nothrow @nogc @property @trusted boolssse3();

Is SSSE3 supported?

pure nothrow @nogc @property @trusted boolsse41();

Is SSE4.1 supported?

pure nothrow @nogc @property @trusted boolsse42();

Is SSE4.2 supported?

pure nothrow @nogc @property @trusted boolsse4a();

Is SSE4a supported?

pure nothrow @nogc @property @trusted boolaes();

Is AES supported

pure nothrow @nogc @property @trusted boolhasPclmulqdq();

Is pclmulqdq supported

pure nothrow @nogc @property @trusted boolhasRdrand();

Is rdrand supported

pure nothrow @nogc @property @trusted boolavx();

Is AVX supported

pure nothrow @nogc @property @trusted boolvaes();

Is VEX-Encoded AES supported

pure nothrow @nogc @property @trusted boolhasVpclmulqdq();

Is vpclmulqdq supported

pure nothrow @nogc @property @trusted boolfma();

Is FMA supported

pure nothrow @nogc @property @trusted boolfp16c();

Is FP16C supported

pure nothrow @nogc @property @trusted boolavx2();

Is AVX2 supported

pure nothrow @nogc @property @trusted boolhle();

Is HLE (hardware lock elision) supported

pure nothrow @nogc @property @trusted boolrtm();

Is RTM (restricted transactional memory) supported

pure nothrow @nogc @property @trusted boolavx512f();

Is AVX512F supported

pure nothrow @nogc @property @trusted boolhasRdseed();

Is rdseed supported

pure nothrow @nogc @property @trusted boolhasSha();

Is SHA supported

pure nothrow @nogc @property @trusted boolamd3dnow();

Is AMD 3DNOW supported?

pure nothrow @nogc @property @trusted boolamd3dnowExt();

Is AMD 3DNOW Ext supported?

pure nothrow @nogc @property @trusted boolamdMmx();

Are AMD extensions to MMX supported?

pure nothrow @nogc @property @trusted boolhasFxsr();

Is fxsave/fxrstor supported?

pure nothrow @nogc @property @trusted boolhasCmov();

Is cmov supported?

pure nothrow @nogc @property @trusted boolhasRdtsc();

Is rdtsc supported?

pure nothrow @nogc @property @trusted boolhasCmpxchg8b();

Is cmpxchg8b supported?

pure nothrow @nogc @property @trusted boolhasCmpxchg16b();

Is cmpxchg8b supported?

pure nothrow @nogc @property @trusted boolhasSysEnterSysExit();

Is SYSENTER/SYSEXIT supported?

pure nothrow @nogc @property @trusted boolhas3dnowPrefetch();

Is 3DNow prefetch supported?

pure nothrow @nogc @property @trusted boolhasLahfSahf();

Are LAHF and SAHF supported in 64-bit mode?

pure nothrow @nogc @property @trusted boolhasPopcnt();

Is POPCNT supported?

pure nothrow @nogc @property @trusted boolhasLzcnt();

Is LZCNT supported?

pure nothrow @nogc @property @trusted boolisX86_64();

Is this an Intel64 or AMD 64?

pure nothrow @nogc @property @trusted boolisItanium();

Is this an IA64 (Itanium) processor?

pure nothrow @nogc @property @trusted boolhyperThreading();

Is hyperthreading supported?

pure nothrow @nogc @property @trusted uintthreadsPerCPU();

Returns number of threads per CPU

pure nothrow @nogc @property @trusted uintcoresPerCPU();

Returns number of cores in CPU

pure nothrow @nogc @property @trusted boolpreferAthlon();

Optimisation hints for assembly code.

For forward compatibility, the CPU is compared against differentmicroarchitectures. For 32-bit x86, comparisons are made againstthe Intel PPro/PII/PIII/PM family.

The major 32-bit x86 microarchitecture 'dynasties' have been:

Intel P6 (PentiumPro, PII, PIII, PM, Core, Core2).
AMD Athlon (K7, K8, K10).
Intel NetBurst (Pentium 4, Pentium D).
In-order Pentium (Pentium1, PMMX, Atom)

Other early CPUs (Nx586, AMD K5, K6, Centaur C3, Transmeta,Cyrix, Rise) were mostly in-order.

Some new processors do not fit into the existing categories:

Intel Atom 230/330 (family 6, model 0x1C) is an in-order core.
Centaur Isiah = VIA Nano (family 6, model F) is an out-of-order core.

Within each dynasty, the optimisation techniques are largelyidentical (eg, use instruction pairing for group 4). Majorinstruction set improvements occur within each dynasty.

Does this CPU perform better on AMD K7 code than PentiumPro..Core2 code?

pure nothrow @nogc @property @trusted boolpreferPentium4();

Does this CPU perform better on Pentium4 code than PentiumPro..Core2 code?

pure nothrow @nogc @property @trusted boolpreferPentium1();

Does this CPU perform better on Pentium I code than Pentium Pro code?

uintstepping;

Warning: This field will be turned into a property in a future release.

Processor type (vendor-dependent).This should be visible ONLY for display purposes.

uintmodel;

Warning: This field will be turned into a property in a future release.

Processor type (vendor-dependent).This should be visible ONLY for display purposes.

uintfamily;

Warning: This field will be turned into a property in a future release.

Processor type (vendor-dependent).This should be visible ONLY for display purposes.

uintnumCacheLevels;

This field has been deprecated. Please usecacheLevels instead.

nothrow @nogc @property @trusted uintcacheLevels();

The number of cache levels in the CPU.

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Library Reference

core.cpuid