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• 2026
• 
  [j62]
  Tong Li,Honglan Jiang,Qin Wang,Jianfei Jiang,Zhigang Mao:
  A power-efficient multiplier with fine-grained power management.Microelectron. J.167:106923 (2026)
• 2025
• 
  [j61]
  Dehua Sun,Wei Chen,Jun He,Yongjian He,Haoqin Jiang,Hong Jiang,Dandan Liu,Lu Li,Min Liu,Zhigang Mao,Chenxue Qu,Linlin Qu,Ziyong Sun,Jianbiao Wang,Wenjing Wu,Xuefeng Wang,Wei Xu,Ying Xing,Chi Zhang,Jingxian Zhang,Lei Zheng,Shihong Zhang,Bo Ye,Ming Guan:
  A novel method for screening malignant hematological diseases by constructing an optimal machine learning model based on blood cell parameters.BMC Medical Informatics Decis. Mak.25(1):72 (2025)
• 
  [j60]
  Ao Liu,Siting Liu,Hui Wang,Qin Wang,Fabrizio Lombardi,Zhigang Mao,Honglan Jiang:
  Low-Power Multiplier Designs by Leveraging Correlations of 2$\times$×2 Encoded Partial Products.IEEE Trans. Computers74(11):3888-3896 (2025)
• 
  [j59]
  Liyan Chen,Pengyu Liu,Dongxu Lyu,Jianfei Jiang,Qin Wang,Zhigang Mao,Naifeng Jing:
  Bridge-NDP: Efficient Communication-Computation Overlap in Near Data Processing System.IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.44(8):2939-2951 (2025)
• 
  [j58]
  Shuya Ji,Weidong Yang,Jianfei Jiang,Naifeng Jing,Honglan Jiang,Zhigang Mao,Qin Wang:
  MACS: A Multidomain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators.IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.44(8):2992-3005 (2025)
• 
  [j57]
  Tong Li,Honglan Jiang,Zhou Wang,Qin Wang,Jianfei Jiang,Zhigang Mao:
  Efficient Extraction and Packing Modules for Posit Multipliers.IEEE Trans. Circuits Syst. II Express Briefs72(11):1765-1769 (2025)
• 
  [j56]
  Zizheng Dong,Shuaipeng Li,Weijia Zhu,Ang Li,Qin Wang,Naifeng Jing,Weiguang Sheng,Jianfei Jiang,Zhigang Mao:
  A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip.IEEE Trans. Very Large Scale Integr. Syst.33(6):1502-1515 (2025)
• 
  [c87]
  Liyan Chen,Jianfei Jiang,Qin Wang,Zhigang Mao,Naifeng Jing:
  MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing.ASP-DAC2025:656-662
• 
  [c86]
  Liyan Chen,Dongxu Lyu,Zhenyu Li,Jianfei Jiang,Qin Wang,Zhigang Mao,Naifeng Jing:
  AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory.DAC2025:1-7
• 
  [c85]
  Tongjing Wu,Xiaolu Hu,Tong Li,Siting Liu,Hui Wang,Weifeng He,Zhigang Mao,Honglan Jiang:
  EPIC: Error PredIction and Correction for Power-Efficient Voltage Underscaling Multiply-Accumulate Unit.DAC2025:1-7
• 
  [c84]
  Xiaolu Hu,Xinkuang Geng,Zhigang Mao,Jie Han,Honglan Jiang:
  A Low-Power Mixed-Precision Integrated Multiply-Accumulate Architecture for Quantized Deep Neural Networks.DATE2025:1-7
• 
  [c83]
  Weidong Yang,Shuya Ji,Jianfei Jiang,Naifeng Jing,Qin Wang,Zhigang Mao,Weiguang Sheng:
  HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler.DATE2025:1-6
• 
  [c82]
  Liyan Chen,Dongxu Lyu,Jianfei Jiang,Qin Wang,Zhigang Mao,Naifeng Jing:
  AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing.HPCA2025:518-532
• 
  [i2]
  Qingyuan Liu,Liyan Chen,Yanning Yang,Haocheng Wang,Dong Du,Zhigang Mao,Naifeng Jing,Yubin Xia,Haibo Chen:
  L3: DIMM-PIM Integrated Architecture and Coordination for Scalable Long-Context LLM Inference.CoRRabs/2504.17584 (2025)
• 2024
• 
  [j55]
  Kunyue Li,Zhengji Zhao,Qixuan Cai,Qin Wang,Naifeng Jing,Zhigang Mao,Jianfei Jiang:
  A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance.Expert Syst. Appl.249:123828 (2024)
• 
  [j54]
  Zihan Zhang,Jianfei Jiang,Qin Wang,Zhigang Mao,Naifeng Jing:
  3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator.IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.43(1):176-188 (2024)
• 
  [j53]
  Chen Yin,Jianfei Jiang,Qin Wang,Zhigang Mao,Naifeng Jing:
  DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating.IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.43(4):1163-1176 (2024)
• 
  [j52]
  Weidong Yang,Yuqing Yang,Shuya Ji,Jianfei Jiang,Naifeng Jing,Qin Wang,Zhigang Mao,Weiguang Sheng:
  RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture.IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.43(10):2854-2867 (2024)
• 
  [j51]
  Pengyu Liu,Ang Li,Liyan Chen,Jianfei Jiang,Qin Wang,Zhigang Mao,Naifeng Jing:
  A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture.IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.43(12):4640-4652 (2024)
• 
  [c81]
  Chen Yin,Jianfei Jiang,Qin Wang,Zhigang Mao,Naifeng Jing:
  SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration.ASPDAC2024:225-230
• 
  [c80]
  Liyan Chen,Jianfei Jiang,Qin Wang,Zhigang Mao,Naifeng Jing:
  Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture.ASPDAC2024:460-465
• 
  [i1]
  Ao Liu,Jie Han,Qin Wang,Zhigang Mao,Honglan Jiang:
  An Architectural Error Metric for CNN-Oriented Approximate Multipliers.CoRRabs/2408.12836 (2024)
• 2023
• 
  [j50]
  Tong Li,Honglan Jiang,Hai Mo,Jie Han,Leibo Liu,Zhi-Gang Mao:
  Approximate Processing Element Design and Analysis for the Implementation of CNN Accelerators.J. Comput. Sci. Technol.38(2):309-327 (2023)
• 
  [j49]
  Chen Yin,Naifeng Jing,Jianfei Jiang,Qin Wang,Zhigang Mao:
  A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration.IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.42(3):874-886 (2023)
• 
  [j48]
  Yuxuan Qin,Chuxiong Lin,Weifeng He,Yanan Sun,Zhigang Mao,Mingoo Seok:
  CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration.IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.42(9):3078-3091 (2023)
• 
  [j47]
  Yanan Sun,Zhi Li,Weiyi Liu,Weifeng He,Qin Wang,Zhigang Mao:
  BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars.IEEE Trans. Circuits Syst. I Regul. Pap.70(5):2048-2061 (2023)
• 
  [c79]
  Xiaoyan Li,Zizheng Dong,Shuaipeng Li,Sai Gao,Jianfei Jiang,Guanghui He,Zhigang Mao:
  MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5.ASICON2023:1-4
• 
  [c78]
  Yuqing Yang,Weidong Yang,Qin Wang,Naifeng Jing,Jianfei Jiang,Zhigang Mao,Weiguang Sheng:
  An Efficient near-Bank Processing Architecture for Personalized Recommendation System.ASP-DAC2023:122-127
• 
  [c77]
  Pengyu Liu,Zihan Zhang,Chen Yin,Liyan Chen,Jianfei Jiang,Qin Wang,Zhigang Mao,Naifeng Jing:
  Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture.FPL2023:116-122
• 
  [c76]
  Jiayu Zhang,Shaojun Cheng,Feng Dong,Ke Chen,Yong Qiao,Zhigang Mao,Jianfei Jiang:
  A Hierarchical Communication Algorithm for Distributed Deep Learning Training.MWSCAS2023:526-530
• 
  [c75]
  Haifeng Xiang,Naifeng Jing,Jianfei Jiang,Hongbo Guo,Weiguang Sheng,Zhigang Mao,Qin Wang:
  RTMDet-R2: An Improved Real-Time Rotated Object Detector.PRCV (12)2023:352-364
• 2022
• 
  [j46]
  Linzhe Li,Liyi Xiao,He Liu,Zhigang Mao:
  Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits.IEEE Access10:64161-64171 (2022)
• 
  [j45]
  Guochao Deng,Qin Wang,Jianfei Jiang,Qirun Hong,Naifeng Jing,Weiguang Sheng,Zhigang Mao:
  A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images.IEEE Geosci. Remote. Sens. Lett.19:1-5 (2022)
• 
  [j44]
  Taozhong Li,Naifeng Jing,Zhigang Mao,Yiran Chen:
  A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM.IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.41(6):1842-1854 (2022)
• 
  [j43]
  Zihan Zhang,Jianfei Jiang,Yongxin Zhu,Qin Wang,Zhigang Mao,Naifeng Jing:
  A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator.IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.41(7):2094-2106 (2022)
• 
  [j42]
  Shuai Yuan,Yanan Sun,Weifeng He,Qianrong Gu,Shi Xu,Zhigang Mao,Shikui Tu:
  MSLM-RF: A Spatial Feature Enhanced Random Forest for On-Board Hyperspectral Image Classification.IEEE Trans. Geosci. Remote. Sens.60:1-17 (2022)
• 
  [j41]
  Taozhong Li,Naifeng Jing,Jianfei Jiang,Qin Wang,Zhigang Mao,Yiran Chen:
  A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.ACM Trans. Design Autom. Electr. Syst.27(6):57:1-57:22 (2022)
• 
  [j40]
  Shengzhao Li,Qin Wang,Jianfei Jiang,Weiguang Sheng,Naifeng Jing,Zhigang Mao:
  An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs.IEEE Trans. Very Large Scale Integr. Syst.30(11):1587-1600 (2022)
• 2021
• 
  [j39]
  Chengbin Duan,Wenli Chen,Shun Yao,Zhigang Mao,Zongming Wang,Bin Hu,Haosen Jiao,Dimin Zhu,Yonghong Zhu,Haijun Wang:
  Automatic Detection for Acromegaly Using Hand Photographs: A Deep-Learning Approach.IEEE Access9:2846-2853 (2021)
• 
  [j38]
  Chuxiong Lin,Weifeng He,Yanan Sun,Bingxi Pei,Pavan Kumar Chundi,Zhigang Mao,Mingoo Seok:
  MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip.IEEE J. Solid State Circuits56(7):2270-2280 (2021)
• 
  [j37]
  Zhuojun Liang,Dongxu Lv,Chao Cui,Hai-Bao Chen,Weifeng He,Weiguang Sheng,Naifeng Jing,Zhigang Mao,Guanghui He:
  A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing.IEEE Trans. Very Large Scale Integr. Syst.29(2):307-320 (2021)
• 
  [c74]
  Zihan Zhang,Jianfei Jiang,Weiguang Sheng,Qin Wang,Zhigang Mao,Naifeng Jing:
  A Mapping Method for Reconfigurable Array based on Decoupled DataFlow.BigDataSecurity2021:180-185
• 
  [c73]
  Chuxiong Lin,Weifeng He,Yanan Sun,Zhigang Mao,Mingoo Seok:
  CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement.DAC2021:1093-1098
• 
  [c72]
  Yuge Chen,Zhongyuan Zhao,Jianfei Jiang,Guanghui He,Zhigang Mao,Weiguang Sheng:
  Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture.DATE2021:124-129
• 
  [c71]
  Chen Yin,Qin Wang,Jianfei Jiang,Weiguang Sheng,Guanghui He,Zhigang Mao,Naifeng Jing:
  Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture.DATE2021:1394-1399
• 2020
• 
  [j36]
  Juhua Luo,Ruiliang Pu,Hongtao Duan,Ronghua Ma,Zhigang Mao,Yuan Zeng,Linsheng Huang,Qitao Xiao:
  Evaluating the influences of harvesting activity and eutrophication on loss of aquatic vegetations in Taihu Lake, China.Int. J. Appl. Earth Obs. Geoinformation87:102038 (2020)
• 
  [j35]
  Yijia Zhang,Weiguang Sheng,Jianfei Jiang,Naifeng Jing,Qin Wang,Zhigang Mao:
  Priority Branches for Ship Detection in Optical Remote Sensing Images.Remote. Sens.12(7):1196 (2020)
• 
  [j34]
  Juhua Luo,Ruiliang Pu,Ronghua Ma,Xiaolong Wang,Xijun Lai,Zhigang Mao,Li Zhang,Zhaoliang Peng,Zhe Sun:
  Mapping Long-Term Spatiotemporal Dynamics of Pen Aquaculture in a Shallow Lake: Less Aquaculture Coming along Better Water Quality.Remote. Sens.12(11):1866 (2020)
• 
  [j33]
  Yanan Sun,Weifeng He,Zhigang Mao,Hailong Jiao,Volkan Kursun:
  Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density.IEEE Trans. Circuits Syst. I Regul. Pap.67-I(7):2431-2441 (2020)
• 
  [j32]
  Zhongyuan Zhao,Weiguang Sheng,Qin Wang,Wenzhi Yin,Pengfei Ye,Jinchao Li,Zhigang Mao:
  Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling.IEEE Trans. Parallel Distributed Syst.31(9):2201-2219 (2020)
• 
  [c70]
  Zihan Zhang,Taozhong Li,Ning Guan,Qin Wang,Guanghui He,Weiguang Sheng,Zhigang Mao,Naifeng Jing:
  Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration.ACM Great Lakes Symposium on VLSI2020:345-350
• 
  [c69]
  Chuxiong Lin,Weifeng He,Yanan Sun,Bingxi Pei,Zhigang Mao,Mingoo Seok:
  25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip.ISSCC2020:394-396

• 2019
• 
  [j31]
  Yanan Sun,Jiawei Gu,Weifeng He,Qin Wang,Naifeng Jing,Zhigang Mao,Weikang Qian,Li Jiang:
  Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.IEEE Trans. Circuits Syst. II Express Briefs66-II(5):753-757 (2019)
• 
  [j30]
  Taozhong Li,Qin Wang,Yongxin Zhu,Jianfei Jiang,Guanghui He,Jing Jin,Zhigang Mao,Naifeng Jing:
  A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations.ACM Trans. Design Autom. Electr. Syst.24(2):25:1-25:22 (2019)
• 
  [c68]
  Jiachen Jiang,Yanan Sun,Weifeng He,Zhigang Mao,Volkan Kursun:
  Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections.ASICON2019:1-4
• 
  [c67]
  Linzhe Li,Liyi Xiao,Jie Li,He Liu,Zhigang Mao:
  Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit.ASICON2019:1-4
• 
  [c66]
  Yanan Sun,Weifeng He,Zhigang Mao,Hailong Jiao,Volkan Kursun:
  Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes.ICEIC2019:1-2
• 
  [c65]
  Zhongyuan Zhao,Hyoukjun Kwon,Sachit Kuhar,Weiguang Sheng,Zhigang Mao,Tushar Krishna:
  mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator.ISPASS2019:282-292
• 
  [c64]
  Yongjie Lu,Yanan Sun,Weifeng He,Zhigang Mao:
  A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency.NANOARCH2019:1-6
• 2018
• 
  [j29]
  Jing Guo,Lei Zhu,Yu Sun,Huiliang Cao,Hai Huang,Tianqi Wang,Chunhua Qi,Rongsheng Zhang,Xuebing Cao,Liyi Xiao,Zhigang Mao:
  Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications.IEEE Trans. Very Large Scale Integr. Syst.26(5):991-994 (2018)
• 
  [c63]
  Zhongyuan Zhao,Yantao Liu,Weiguang Sheng,Tushar Krishna,Qin Wang,Zhigang Mao:
  Optimizing the data placement and transformation for multi-bank CGRA computing system.DATE2018:1087-1092
• 
  [c62]
  Shuai Xie,Zhongyuan Zhao,Weiguang Sheng,Qin Wang,Zhigang Mao:
  MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs.ReConFig2018:1-8
• 2017
• 
  [j28]
  Qin Wang,Zhenyang Chen,Jianfei Jiang,Zheng Guo,Zhigang Mao:
  Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC.Integr.59:23-30 (2017)
• 
  [j27]
  Wei Jin,Guanghui He,Weifeng He,Zhigang Mao:
  A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras.Integr.59:206-217 (2017)
• 
  [j26]
  Wei Jin,Seongjong Kim,Weifeng He,Zhigang Mao,Mingoo Seok:
  Near- and Sub-V_t Pipelines Based on Wide-Pulsed-Latch Design Techniques.IEEE J. Solid State Circuits52(9):2475-2487 (2017)
• 
  [j25]
  Yanan Sun,Weifeng He,Zhigang Mao,Volkan Kursun:
  Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic.Microelectron. J.62:12-20 (2017)
• 
  [j24]
  Wei Jin,Seongjong Kim,Weifeng He,Zhigang Mao,Mingoo Seok:
  In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations.IEEE Trans. Very Large Scale Integr. Syst.25(3):1032-1043 (2017)
• 
  [j23]
  Jing Guo,Lei Zhu,Wenyi Liu,Hai Huang,Shanshan Liu,Tianqi Wang,Liyi Xiao,Zhigang Mao:
  Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology.IEEE Trans. Very Large Scale Integr. Syst.25(5):1593-1600 (2017)
• 
  [c61]
  Yanan Sun,Weifeng He,Zhigang Mao,Hailong Jiao,Volkan Kursun:
  Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors.ASICON2017:908-911
• 
  [c60]
  Shanshan Liu,Liyi Xiao,Xuebing Cao,Zhigang Mao:
  Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability.ASP-DAC2017:87-92
• 
  [c59]
  Zhongyuan Zhao,Weiguang Sheng,Weifeng He,Zhigang Mao,Zhaoshi Li:
  A static-placement, dynamic-issue framework for CGRA loop accelerator.DATE2017:1348-1353
• 
  [c58]
  Shanshan Liu,Liyi Xiao,Jie Li,Yihan Zhou,Zhigang Mao:
  Low redundancy matrix-based codes for adjacent error correction with parity sharing.ISQED2017:76-80
• 2016
• 
  [j22]
  Liang Hong,Wei-Feng He,Guanghui He,Zhigang Mao:
  Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding.IEICE Electron. Express13(6):20160019 (2016)
• 
  [j21]
  Zhiting Yan,Guanghui He,Weifeng He,Shuaijie Wang,Zhigang Mao:
  High performance parallel turbo decoder with configurable interleaving network for LTE application.Integr.52:77-90 (2016)
• 
  [j20]
  Jianfei Jiang,Zhigang Mao,Weiguang Sheng,Qin Wang,Weifeng He:
  Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects.J. Circuits Syst. Comput.25(10):1650121:1-1650121:31 (2016)
• 
  [j19]
  Weiguang Sheng,Jianfei Jiang,Zhigang Mao:
  Parallel SER analysis for combinational and sequential standard cell circuits.Microelectron. J.50:8-19 (2016)
• 
  [j18]
  Shanshan Liu,Liyi Xiao,Zhigang Mao:
  Extend orthogonal Latin square codes for 32-bit data protection in memory applications.Microelectron. Reliab.63:278-283 (2016)
• 
  [c57]
  Wei Jin,Seongjong Kim,Weifeng He,Zhigang Mao,Mingoo Seok:
  A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines.A-SSCC2016:129-132
• 
  [c56]
  Naifeng Jing,Taozhong Li,Zhongyuan Zhao,Wei Jin,Yanan Sun,Weifeng He,Zhigang Mao:
  Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory.FPT2016:233-236
• 2015
• 
  [j17]
  Jianfei Jiang,Weifeng He,Jizeng Wei,Qin Wang,Zhigang Mao:
  Design optimization for capacitive-resistively driven on-chip global interconnect.IEICE Electron. Express12(8):20150111 (2015)
• 
  [j16]
  Zhiting Yan,Guanghui He,Weifeng He,Zhigang Mao:
  Improved Iterative Receiver for Co-channel Interference Suppression in MIMO-OFDM Systems.IEICE Trans. Fundam. Electron. Commun. Comput. Sci.98-A(2):776-782 (2015)
• 
  [j15]
  Zhiting Yan,Guanghui He,Yifan Ren,Weifeng He,Jianfei Jiang,Zhigang Mao:
  Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing.IEEE Trans. Circuits Syst. I Regul. Pap.62-I(11):2706-2717 (2015)
• 
  [j14]
  Jing Guo,Liyi Xiao,Tianqi Wang,Shanshan Liu,Xu Wang,Zhigang Mao:
  Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology.IEEE Trans. Reliab.64(2):596-602 (2015)
• 
  [c55]
  Sai Hu,Qin Wang,Zheng Guo,Jing Xie,Zhigang Mao:
  Fault detection and redundancy design for TSVs in 3D ICs.ASICON2015:1-4
• 
  [c54]
  Jiayi Hu,Qin Wang,Jianfei Jiang,Jing Xie,Zhigang Mao:
  A crosstalk avoidance scheme based on re-layout of signal TSV.ASICON2015:1-4
• 
  [c53]
  Shanshan Liu,Liyi Xiao,Jing Guo,Zhigang Mao:
  Fault Secure Encoder and Decoder Designs for Matrix Codes.CAD/Graphics2015:181-185
• 
  [c52]
  Naifeng Jing,Jiacheng Zhou,Jianfei Jiang,Xin Chen,Weifeng He,Zhigang Mao:
  Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs.ICCAD2015:764-769
• 
  [c51]
  Jianfei Jiang,Weiguang Sheng,Qin Wang,Zhigang Mao:
  A contactless testing methodology for pre-bond interposer.MWSCAS2015:1-4
• 
  [c50]
  Weiguang Sheng,Zhongyuan Zhao,Zhigang Mao:
  Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework.PRDC2015:325-326
• 
  [c49]
  Zhongyuan Zhao,Weiguang Sheng,Naifeng Jing,Weifeng He,Zhigang Mao:
  Resource-saving compile flow for coarse-grained reconfigurable architectures.ReConFig2015:1-8
• 2014
• 
  [j13]
  Zhiting Yan,Guanghui He,Xi Chen,Weifeng He,Zhigang Mao:
  Improved Max-Log-MAP BICM-IDD receiver for MIMO systems.IEICE Electron. Express11(21):20140800 (2014)
• 
  [j12]
  Jing Guo,Liyi Xiao,Zhigang Mao:
  Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology.IEEE Trans. Circuits Syst. I Regul. Pap.61-I(7):1994-2001 (2014)
• 
  [j11]
  Jing Guo,Liyi Xiao,Zhigang Mao,Qiang Zhao:
  Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code.IEEE Trans. Very Large Scale Integr. Syst.22(1):127-135 (2014)
• 
  [c48]
  Ziyou Yao,Weifeng He,Liang Hong,Guanghui He,Zhigang Mao:
  Area and throughput efficient IDCT/IDST architecture for HEVC standard.ISCAS2014:2511-2514
• 2013
• 
  [j10]
  Liang Hong,Weifeng He,Hui Zhu,Zhigang Mao:
  A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard.IEICE Electron. Express10(9):20130210 (2013)
• 
  [j9]
  Jing Guo,Liyi Xiao,Zhigang Mao,Qiang Zhao:
  Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs.IEEE Micro33(6):66-74 (2013)
• 
  [c47]
  Haopeng Liu,Weiguang Sheng,Weifeng He,Zhigang Mao:
  Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor.ASICON2013:1-4
• 
  [c46]
  Jieliang Lu,Qin Wang,Jing Xie,Zhigang Mao:
  TSVs-aware floorplanning for 3D integrated circuit.ASICON2013:1-4
• 
  [c45]
  Zheng Tang,Jing Xie,Zhigang Mao:
  A novel architecture scheme with adaptive pipeline coupling technique for DSP processor design.ASICON2013:1-4
• 
  [c44]
  Yuxiao Ling,Zheng Guo,Zhimin Zhang,Zhigang Mao,Zeleng Zhuang:
  A Block Cipher Circuit Design against Power Analysis.CIS2013:449-453
• 
  [c43]
  Naifeng Jing,Yao Shen,Yao Lu,Shrikanth Ganapathy,Zhigang Mao,Minyi Guo,Ramon Canal,Xiaoyao Liang:
  An energy-efficient and scalable eDRAM-based register file architecture for GPGPU.ISCA2013:344-355
• 
  [c42]
  Liang Hong,Weifeng He,Hui Zhu,Zhigang Mao:
  A cost effective 2-D adaptive block size IDCT architecture for HEVC standard.MWSCAS2013:1290-1293
• 
  [c41]
  Mingyuan Ren,Xiaowei Liu,Wen Zuo,Zhigang Mao:
  Analysis of electromechanical interface model for liquid floated micro-gyroscope.NEMS2013:799-802
• 
  [c40]
  Zhi Yue,Guanghui He,Jiangpeng Li,Jun Ma,Zhigang Mao:
  A soft-output parallel stack algorithm for MIMO detection.SiPS2013:30-35
• 2012
• 
  [j8]
  Naifeng Jing,Ju-Yueh Lee,Zhe Feng,Weifeng He,Zhigang Mao,Lei He:
  SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms.ACM Trans. Design Autom. Electr. Syst.18(1):13:1-13:18 (2012)
• 
  [c39]
  Weiguang Sheng,Weifeng He,Jianfei Jiang,Zhigang Mao:
  Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm.IPDPS Workshops2012:425-430
• 
  [c38]
  Jianfei Jiang,Wei-Guang Sheng,Zhi-Gang Mao,Wei-Feng He:
  A pre-emphasis circuit design for high speed on-chip global interconnect.ISCAS2012:2941-2944
• 
  [c37]
  Bingjing Ge,Naifeng Jing,Weifeng He,Zhigang Mao:
  Contention and energy aware mapping for real-time applications on Network-on-Chip.ISOCC2012:72-76
• 
  [c36]
  Pengfei Gou,Bing Yang,Mingyan Yu,Zhigang Mao:
  Novel O-GEHL Based Hyperblock Predictor for EDGE Architectures.NAS2012:172-180
• 2011
• 
  [j7]
  Xin-chun Wu,Jinxiang Wang,Bin Zhou,Zhigang Mao,Zhiqiang Gao:
  Companding schemes based on transforming signal statistics into trigonal distributions for PAPR reduction in OFDM systems.Int. J. Commun. Syst.24(6):776-788 (2011)
• 
  [j6]
  Xin-chun Wu,Bin Zhou,Jinxiang Wang,Zhigang Mao:
  Low Complexity Time Domain Interleaved Partitioning Partial Transmit Sequence Scheme for Peak-to-Average Power Ratio Reduction of Orthogonal Frequency Division Multiplexing Systems.Wirel. Pers. Commun.60(2):277-294 (2011)
• 
  [c35]
  Jin Huang,Jing Xie,Zhigang Mao:
  A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications.ASICON2011:192-195
• 
  [c34]
  Zaixiao Zheng,Zhigang Mao,Jianfei Jiang:
  An efficient 90nm technology-node GHz transceiver of on-chip global interconnect.ASICON2011:649-652
• 
  [c33]
  Yucheng Liu,Jing Xie,Zhigang Mao:
  A reconfigurable linear array processor architecture for data parallel and computation intensive applications.ASICON2011:783-786
• 
  [c32]
  Yifan Zhou,Weiguang Sheng,Xie Liu,Weifeng He,Zhigang Mao:
  Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm.ASICON2011:941-944
• 
  [c31]
  Naifeng Jing,Ju-Yueh Lee,Chun Zhang,Jiarong Tong,Zhigang Mao,Lei He:
  Fault modeling and characteristics of SRAM-based FPGAs (abstract only).FPGA2011:279
• 
  [c30]
  Naifeng Jing,Ju-Yueh Lee,Zhe Feng,Weifeng He,Zhigang Mao,Shi-Jie Wen,Rick Wong,Lei He:
  Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.FPL2011:282-285
• 
  [c29]
  Naifeng Jing,Ju-Yueh Lee,Weifeng He,Zhigang Mao,Lei He:
  Mitigating FPGA interconnect soft errors by in-place LUT inversion.ICCAD2011:582-586
• 
  [c28]
  Xu Wang,Jianfei Jiang,Zhi-Gang Mao,Bingjing Ge,Xinglong Zhao:
  A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme.ICECS2011:528-531
• 
  [c27]
  Yuliang Tao,Guanghui He,Weifeng He,Qin Wang,Jun Ma,Zhigang Mao:
  Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems.ISCAS2011:1487-1490
• 
  [c26]
  Li Xie,Weifeng He,Naifeng Jing,Zhigang Mao:
  A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor.ISCAS2011:1952-1955
• 
  [c25]
  Shuaijie Wang,Jun Ma,Guanghui He,Zhigang Mao:
  Generalized interleaving network based on configurable QPP architecture for parallel turbo decoder.SiPS2011:204-209
• 
  [c24]
  Jianpeng Yu,Jun Ma,Zhigang Mao:
  Parallel SFSD MIMO detection with SOFT-HARD combination enumeration.SiPS2011:228-233
• 
  [c23]
  Wei Jin,Sheng Lu,Weifeng He,Zhigang Mao:
  A 230mV 8-bit sub-threshold microprocessor for wireless sensor network.VLSI-SoC2011:126-129
• 
  [c22]
  Naifeng Jing,Weifeng He,Zhigang Mao:
  A general statistical estimation for application mapping in Network-on-Chip.VLSI-SoC2011:172-175
• 
  [c21]
  Jing Xie,Huimin Xing,Zhigang Mao:
  On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array system.VLSI-SoC2011:176-179
• 
  [c20]
  Jianfei Jiang,Xu Wang,Wei-Guang Sheng,Wei-Feng He,Zhi-Gang Mao:
  A clock-less transceiver for global interconnect.VLSI-SoC2011:184-187
• 
  [c19]
  Wei Jin,Sheng Lu,Weifeng He,Zhigang Mao:
  Robust design of sub-threshold flip-flop cells for wireless sensor network.VLSI-SoC2011:440-443
• 2010
• 
  [j5]
  Xin-chun Wu,Jinxiang Wang,Zhigang Mao,Jianwei Zhang:
  Conjugate Interleaved Partitioning PTS Scheme for PAPR Reduction of OFDM Signals.Circuits Syst. Signal Process.29(3):499-514 (2010)
• 
  [j4]
  Naifeng Jing,Weifeng He,Yongxin Zhu,Zhigang Mao:
  Statistical estimation and evaluation for communication mapping in Network-on-Chip.Integr.43(2):220-229 (2010)
• 
  [c18]
  Naifeng Jing,Weifeng He,Zhigang Mao:
  Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array.SoCC2010:260-265
• 
  [c17]
  Weifeng He,Weiwei Chen,Zhigang Mao:
  An efficient VLSI architecture for extended variable block sizes motion estimation.SoCC2010:347-350

• 2009
• 
  [c16]
  Weiguang Sheng,Liyi Xiao,Zhigang Mao:
  Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.DAC2009:502-507
• 
  [c15]
  Naifeng Jing,Zhigang Mao,Yongxin Zhu:
  Statistical Estimation for Total Communication Load in Application-Specific Network-on-Chip.ICESS2009:109-114
• 2008
• 
  [c14]
  Weiguang Sheng,Liyi Xiao,Zhigang Mao:
  An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling.DELTA2008:587-591
• 
  [c13]
  Majun Zheng,Jing Xie,Zhigang Mao,Yongxin Zhu:
  A Hybrid Anti-Collision Algorithm for RFID with Enhanced Throughput and Reduced Memory Consumption.EUC (1)2008:259-265
• 
  [c12]
  Weiguang Sheng,Liyi Xiao,Zhigang Mao:
  A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis.ICECS2008:766-769
• 
  [c11]
  Weiguang Sheng,Liyi Xiao,Zhigang Mao:
  Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns.PRDC2008:17-23
• 2007
• 
  [c10]
  Wenbiao Zhou,Yan Zhang,Zhigang Mao:
  A Link-Load Balanced Low Energy Mapping and Routing for NoC.ICESS2007:59-66
• 
  [c9]
  Wei-Feng He,Zhi-Gang Mao:
  An Improved Frame-Level Pipelined Architecture for High Resolution Video Motion Estimation.ISCAS2007:1381-1384
• 
  [c8]
  Wei-Feng He,Meng-Lian Zhao,Chi-Ying Tsui,Zhi-Gang Mao:
  A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation.VLSI Design2007:830-835
• 2006
• 
  [j3]
  Peng Liu,Yan Zhang,Zhigang Mao:
  A Restoration Algorithm for Images Contaminated by Impulse Noise.J. Comput. Res. Dev.43(11):1939-1946 (2006)
• 
  [j2]
  Wei Zhong,Zhigang Mao:
  Efficient time-domain residual ISI cancellation for OFDM-based WLAN systems.IEEE Trans. Consumer Electron.52(2):321-326 (2006)
• 
  [c7]
  Wenbiao Zhou,Yan Zhang,Zhigang Mao:
  Pareto based Multi-objective Mapping IP Cores onto NoC Architectures.APCCAS2006:331-334
• 
  [c6]
  Wei Zhong,Zhigang Mao:
  Design and VLSI Architecture of a Channel Equalizer Based on Adaptive Modulation for IEEE 802.11a WLAN.APCCAS2006:1699-1702
• 2005
• 
  [c5]
  Weifeng He,Yunlong Bi,Zhigang Mao:
  Efficient frame-level pipelined array architecture for full-search block-matching motion estimation.ISCAS (3)2005:2887-2890
• 2004
• 
  [c4]
  Hui Wang,Zhigang Mao:
  An adaptive motion estimation algorithm based on evolution strategies.ICASSP (3)2004:353-356
• 
  [c3]
  Hui Wang,Zhigang Mao:
  An adaptive motion estimation algorithm based on evolution strategies with correlated mutations.ICIP2004:1469-1472
• 2000
• 
  [j1]
  Liu Songyan,Zhigang Mao,Yizheng Ye:
  Implementation of Java Card Virtual Machine.J. Comput. Sci. Technol.15(6):591-596 (2000)

• 1999
• 
  [c2]
  Zulan Huang,Yizheng Ye,Zhigang Mao:
  A New Algorithm for Retiming-Based Partial Scan.Asian Test Symposium1999:327-
• 1998
• 
  [c1]
  Pingying Zeng,Zhigang Mao,Yizheng Ye,Yuliang Deng:
  Test Pattern Generation for Column Compression Multiplier.Asian Test Symposium1998:500-503

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