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Schloss Dagstuhl - Leibniz Center for Informatics
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ITC 2004: Charlotte, NC, USA

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    Cover

    Introduction

    Session 1:Plenary

    Session 2:Microprocessor Test

    Session 3:Logic BIST

    Session 4:BIST for Jitter

    Session 5:Memory Testing

    Session 6:Failure Characterization Methods for IC Diagnosis

    Session 7:Board and System Test:At-Speed and Bounce-Free

    Session 8:Methods and Strategies for Optimal Test

    Session 9:In Search of Small Delay Defects

    Session 10:Mixed-Signal BIST and DFT

    Session 11:Advances in Testing for Defects

    Session 12:Advances in DFT

    Session 13:Board and System Test:Board Test Effectiveness

    Session 14:Developments in ATE Software Standards

    Session 15:Handling of Unknowns

    Session 16:Emerging Technologies Fault Modeling and Tolerance

    Session 17:Advances in Diagnosis

    Session 18:Test Economics

    Session 19:Board and System Test:Extending Boundary-Scan to RF and HS Serial Testing

    Session 20:Squeezing the Picoseconds

    Session 21:ATPG/FAULT Simulation Specialties

    Session 22:Interconnect Testing and Fault Diagnosis in FPGAS

    Session 23:Industry Case Studies in Testing

    Session 24:Lecture Series - Test Trends and Challenges

    Session 25:Board and System Test:System and Field Test

    Session 26:ATE for the Fastest Devices

    Session 27:SoC:Mixed Signals, Size and Speed

    Session 28:RF Testing

    Session 29:State Space Exploration and Test Generation

    Session 30:SoC Test Case Studies

    Session 31:Board and System Test:Board and System-Level BIST Techniques

    Session 32:Test of Digital, Analog and MEMS C

    Session 33:Test Compression

    Session 34:Mixed-Signal Test Techniques

    Session 35:Embedded Memories BIST and Repair

    Session 36:Delay Testing

    Session 37:Application Series - Board and System-Level DFT and Test

    Session 38:Formalizing and Simulating ATE

    Session 39:Testing for Speed - New and Practical Methods

    Session 40:Picosecond Jitter Testing

    Session 41:Application Series - Wafer Probe Technology

    Session 42:Wrappers and More

    Session 43:Design-for-Availability

    Session 44:Advances in Tester Architecture

    Session 45:Advances in Delay Testing

    Session 46:Application Series - Jitter in Test

    Session 47:On-Line Testing and Fault Tolerance at Low Cost

    Session 48:Advances in SoC Test

    Session 49:ADC Testing

    Panel 1:Open Architecture ATE:Reality or Dream?

    Panel 2:Security vs. Test Quality:Can we only have one at a time?

    Panel 3:Glamorous Analog Testability - We Already Test them and Ship Them... So What is the Problem?

    Panel 4:100 DPM in Nanometer Technology - Is it Achievable?

    Panel 5:What Do You Mean My Board Test Stinks?

    Panel 6:DUDE! Where's My Data? - Cracking Open the Hermetically Sealed Tester

    Panel 7:Cost of Test:Taking Control

    Panel 8:Is "Design-to-Production" The Ultimate Answer for Jitter, Noise, and BER Challenges for Multi-GB/S ICs?

    Panel 9:Diagnosis Meets Physical Failure Analysis:How Long Can We Succeed?

    Panel 10:Investment vs. Yield Relationship for Memories in SoC

    ITC 2003 Best Paper

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