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Schloss Dagstuhl - Leibniz Center for Informatics
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EDAC 1994: Paris, France

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    Session 1A:Processor Architecture

    Session 1B:System Level Transformation and Micro Code Generation

    Session 1C:Testing Sequential Circuits.

    Session 2A:System Design and Mixed A/D Synthesis

    Session 2B:Circuit Optimization and Partitioning

    Session 2C:BIST Techniques

    Session 3A:Finite State Machine Verification

    Session 3C:Fault Modeling

    Session 4A:Synchronous Finite State Machines

    Session 4B:New BDD-Concepts

    Session 4C:Applications of Boundary Scan

    Session 5A:DSP Implementations

    Session 5B:Algorithmic Transformations in High-Level Synthesis

    Session 5C:DFT for Delay Faults and Sequential Machines

    Session 6A:Estimation During High-Level Synthesis

    Session 6B:Towards Statistical and High-Level Timing Analysis

    Session 6C:Bridging Faults in Testing

    Session 7A:Specification and Synthesis of System Interfaces

    Session 7C:Routing

    Session 8A:Performance Issues in Physical Design

    Session 8C:Various Views on Testing Efficiency

    Session 9A:Design Methodologies for the System-Level

    Session 9B:Applications of Scheduling in High-Level Synthesis

    Session 9C:Delay Test

    Session 10A:Tools and Methods for Analogue System Design

    Session 10B:Logic, Circuit, and Yield Simulation Technologies

    Session 10C:DFT for Datapaths, Controllers, and Arrays

    Session 11A:Framework Services for Productivity Improvement

    Session 11B:Techniques and Applications for BDDs

    Session 11C:High-Level Verification

    Poster Session

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    dblp was originally created in 1993 at:

    University of Trier  

    since 2018, dblp has been operated and maintained by:

    Schloss Dagstuhl - Leibniz Center for Informatics  

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