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Schloss Dagstuhl - Leibniz Center for Informatics
For some weeks now, the dblp team has been receiving anexceptionally high number of support and error correction requests from the community. While we are grateful and happy to process all incoming emails, please assume thatit will currently take us several weeks to read and address your request. Most importantly,please refrain from sending your request multiple times. This will not advance your issue and will only complicate and extend the time required to address it. Thank you for your understanding.
Joint Declaration:The freedom of science is at the heart of liberal, democratic societies. Without this freedom, it is impossible for scientific efforts to be geared toward gaining knowledge and facts. It is therefore extremely worrying that the scientific freedom is coming under increasing pressure in various regions of the world.(read more)
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DATE 2006: Munich, Germany

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    Keynote Addresses

    Allocation and scheduling for MPSoCs and NoCs

    Power grid and large interconnect network analysis

    Interactive presentation

    On-line testing and fault tolerance

    Interactive presentation

    Chip design records

    Model based design and test

    Transaction level modelling based validation

    Application-specific network on chip design

    Interactive presentation

    Methods and tools for systematic analogue design

    Interactive presentation

    Soft error analysis and concurrent testing

    System design records

    Application-specific architectures

    System level performance analysis

    Hot topic - 'Network':the Next 'Big Idea' in design? network paradigms in systems, sensors, and silicon

    Advances in verification and synthesis for analogue design automation

    Interactive presentation

    Advanced SoC test scheduling

    Interactive presentation

    Design methodologies for emerging technologies

    Interactive presentation

    Processor and memory design

    Spatial and temporal mapping for reconfigurable computing

    DFM/DFY design for manufacturability and yield

    Analogue and mixed-signal design

    Interactive presentation

    Processor self-test and fault diagnosis

    Interactive presentation

    Scheduling for real-time and energy

    System level modelling and simulation

    Interactive presentation

    Hot topic:system level design of SoC (4G wireless special day)

    Power-efficient hardware/software architectures

    Interactive presentation

    Timing and noise analysis

    Interactive presentation

    Test and reliability challenges in automotive microelectronics

    Communication methods and networking in automotive systems

    System level modelling

    Interactive presentation

    Hot topic:architectures and NoC (4G wireles special day)

    Keynote

    Low power embedded architectures and platforms

    Interactive presentation

    Transistor and gate level simulation

    Interactive presentation

    SoC targeted mixed-signal test solutions

    Interactive presentation

    System optimisation with embedded software

    Interactive presentation

    Communication-centric system-level synthesis for MPSoC

    Interactive presentation

    Hot topic:cross disciplinary aspects (4G wireless special day)

    Techniques for architecture exploration and characterisation

    Interactive presentation

    Clocks and routing

    Reliability issues for nanotechnology circuits

    Interactive presentation

    Architectures for predictable real-time computing and communication

    Modern decision procedures

    Applications, architectures, design methodology and tools for MPSoc

    Thermal aspects of low power design

    Leakage and dynamic power aware logic design

    Interactive presentation

    Advanced topics in physical design

    Advances in defect modelling and detection

    Code and data layout optimisations for embedded software

    Interactive presentation

    Advanced reconfigurable architectures and applications

    Hot topic - introduction to and applications for wireless sensor networks (WSN) - (wireless sensor networks special day)

    Leakage-aware circuit design

    Coverage based validation

    Interactive presentation

    Test data compression

    Interactive presentations

    Resource constrained scheduling

    Sequential optimisation, clocking and Boolean matching

    Hot topic - design, verification, deployment and test of WSN systems

    Keynote

    Power reduction at circuit level

    Semi-formal validation methods

    Interactive presentation

    Testing memories, FPGAs and networks-on-a-chip

    Interactive presentation

    Architectural level synthesis

    Interactive presentation

    Advances in state space exploration

    Interactive presentations

    Low-power design tools:are EDA vendors taking this matter seriously?

    System level verification

    Memory testing and test set improvement

    Reliable microarchitectures

    Progress in logic and arithmetic circuit optimisation

    MPSoC modelling and design

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    dblp was originally created in 1993 at:

    University of Trier  

    since 2018, dblp has been operated and maintained by:

    Schloss Dagstuhl - Leibniz Center for Informatics  

    the dblp computer science bibliography is funded and supported by:

    BMBF  RLP  SL  Leibniz  DFG  NFDI  
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