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Schloss Dagstuhl - Leibniz Center for Informatics
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31st DAC 1994: San Diego, California, USA

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    Software & Instruction Set Synthesis

    Transition Densities for Sequential Systems

    CAD for Analog and High-Performance Digital Circuits

    Management of Electronic Design Automation

    Panel

    Asynchronous Synthesis

    New Developments in Design for Test

    Timing Analysis

    Managing The Design Process

    Estimation & Synthesis of Memory Structures

    Intellectual Property

    Panel

    Technology-Driven Routing

    Panel

    data-Path Synthesis & Test

    Topics in Verification and Diagnosis

    FPGA Partitioning and Optimization

    Design Implementation

    BDD Techniques and Formal Verification

    Panel

    FPGA Placement & Routing

    Formal Verification

    Panel

    Layout and Technology Dependent Synthesis

    Delay and Self Test

    Routing for High Performance

    Panel

    Logic Synthesis

    Tutorial:Hardware-Software Co-Design

    Design Representations and Data Structures for High Level Design

    Design Methodology

    Scheduling

    CAD Algorithms in Non-CAD Problems

    Fault Simulation and Diagnosis

    World Class Electronic Design Methodologies I

    New Ideas in High-level Synthesis

    Panel

    Electrical and Thermal Analysis

    World Class Design Methodologies II

    Formal Verification of Systems

    Interconnect Analysis

    Circuit Partitioning

    Panel

    Sequential Synthesis

    New Techniques in Test Generation

    Discrete Simulation

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    dblp was originally created in 1993 at:

    University of Trier  

    since 2018, dblp has been operated and maintained by:

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