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Why there is Missing location assignment warnings on hps_io interfaces (SDMMC, UART, I3C) in Quartus® Prime Pro Edition Software version 25.1.1 and earlier?
Description Due to a problem in Quartus® Prime Pro Edition Software v25.1.1 and earlier. You might see the warnings messages “Missing location assignment” on some of the hps_io interfaces due to the mismatch interface name. Resolution This problem is resolved in Quartus® Prime Pro Edition Software v25.3.What Agilex™ 7 FPGA configuration scheme should be used to ensure that the PCI Express* link active time of 120ms is met?
Description To meet the PCIe* spec requirement of 120 ms, the PCIe* REFCLK needs to be running prior to configuring the device, you must specify the OSC_CLK_1 pin as 25 MHz, 100 MHz, or 125 MHz, and use AS x4 Fast Mode configuration with an AS_CLK clock set to 166 MHz. Note: For PCIe designs including Configuration via Protocol (CvP), Altera recommends you to use Micron* QSPI flash in order to load the initial configuration firmware faster to meet the PCIe wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Altera recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enters link training state before PERST# is deasserted. This should be considered for closed-systems only. Agilex™ 7 FPGA Device Configuration via Protocol (CvP) Implementation User Guide Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi Channel DMA FPGA IP for PCI Express* P-Tile Avalon® Streaming IP for PCI Express* R-Tile Avalon® Streaming IP for PCI Express* AXI Streaming IP for PCI Express* AXI Multichannel DMA IP for PCIe*Why does GD55LB02GE QSPI flash fail in Linux* in FPGA SoC device?
Description If you use Linux* version between socfpga-6.0 and socfpga-6.12.43-lts with GD55LB02GE QSPI flash, you may fail to mount the file system in Linux if it’s stored in GD55LB02GE. This is caused by the gigadevice.c in these versions. Resolution This issue is fixed in socfpga-6.12.43-lts and afterwards. You can upgrade Linux source code to this version, or comment out the GD55LB02GE entry in gigadevice.c in old versions.Why does Agilex™ 5 FPGA ES fails to boot from SDCard and eMMC devices in SDR104, HS400 and HS200 modes?
Description Due to a problem that is under investigation, the Agilex™ 5 FPGA ES (Engineering sample) devices may fail to boot from SD Card in SDR104 mode and from eMMC in HS400 and HS200 modes. The failure is observed in U-Boot and Linux*. In U-Boot, the signature of the failure can be seen from instability when loading any component from the device. In Linux, the failure signature is observed from ‘Buffer I/O Error on dev mmcblk0’ errors when accessing the device. Resolution At this time, there is no workaround for this problem, and it’s recommended to switch to the Agilex™ 5 FPGA Production device, in which this problem does not occur.Why are the R-Tile AXI Multichannel DMA IP Design Example DMA Queues stuck when the Gen5 IP configuration links downgrade to Gen4 or lower speeds?
Description Due to a problem in the Quartus® Prime Pro software version 25.3.1 and earlier, the AXI Multichannel DMA IP Queues will stick if the Gen5 configuration of the IP is link downgrades to Gen4 or lower. For example in the Gen5 IP is used in a Gen4 system. Resolution To fix this problem in Quartus® Prime Pro software version 25.3.1 please install patch 1.01 below. This problem is scheduled to be fix in a future release of the Quartus® Prime Pro software. IP Core AXI Multichannel DMA IP for PCI Express*Why do I see compilation failure in the design using F-tile Ethernet Hard IP at 25GE-1 variant for non-MAC PCS direct mode with Firecode FEC enabled in the Quartus® Prime Pro Edition software version 25.3?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see compilation failure in the design using F-tile Ethernet Hard IP at 25GE-1 variant for non-MAC PCS direct mode with Firecode FEC enabled. This is because the Firecode FEC isn’t supported in F-tile Ethernet Hard IP at 25GE-1 variant for non-MAC PCS direct mode. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.3.1.Why does Quartus® Prime Pro Edition report Critical Warning (22976) during the QTLG stage for F-Tile IPs not explicitly configured for Dynamic Reconfiguration when the F-Tile Dynamic Reconfiguration Suite IP is included in the same project?
Description In the Quartus® Prime Pro Edition software version 25.3.1, Critical Warning (22976) may be reported for non-Dynamic Reconfiguration F-Tile protocol IPs when they are instantiated in a design that also contains Dynamic Reconfiguration F-Tile IPs. This warning may appear even when Dynamic Reconfiguration is not required or intended for the non-DR F-Tile IPs. The warning message typically appears as follows: Critical Warning(22976): Dynamic Reconfiguration controller IP specification is missing for IP or IPs {IP_PATH}. Use IP_COLOCATE assignment to specify a Dynamic Reconfiguration controller IP. This warning does not affect design functionality or correctness. It is reported due to how Quartus® Prime Pro Edition software checks for Dynamic Reconfiguration controller assignments when both Dynamic Reconfiguration and non-Dynamic Reconfiguration F-Tile IPs are present in the same design. Resolution There is currently no workaround to suppress Critical Warning(22976) in the Quartus Prime Pro Edition software. If Dynamic Reconfiguration is not required for the IP reporting this warning, this warning can be safely ignored. This is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does FPGA configuration (Phase 2) fail in HPS first boot mode on Agilex™ 5 and Agilex™ 3 SoC FPGAs when using Quartus® Prime Pro Edition Software version 25.3.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version 25.3.1, Phase 2 configuration (FPGA fabric configuration from HPS) may fail on Agilex™ 5 and Agilex™ 3FPGA devices when Phase 1 and Phase 2 bitstreams originate from different designs or design revisions. This is caused by HPS IO hash mismatches between compilations. Resolution To work around this problem, download and install the patch below. You must recompile both the design generating the Phase 1 bitstream and the design generating the Phase 2 bitstream using the patched version of Quartus® Prime Pro Edition Software version 25.3.1. Additional Information HPS IO hash mismatches can also occur for other reasons independent of this Quartus® Prime Pro Edition Software problem. For more information about other potential causes and how to avoid them, refer to the HPS IO Hash Compatibility section in the Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCsWhy does the Timing Analyzer report an unconstrained clock on the internal state signal when using the Generic Serial Flash Interface IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and earlier, you might see that the Timing Analyzer report an unconstrained clock on the internal state signal below, when using the Generic Serial Flash Interface (GSFI) IP. <instance_path>|intel_generic_serial_flash_interface_top_0|serial_flash_inf_cmd_gen_inst|state[0] Adding a create_generated_clock constraint removes the unconstrained clock report but introduces setup timing violations because the clock relationship is inferred as zero, making timing closure unachievable in Quartus® Prime Pro Edition Software version 25.1.1. Resolution There is no reliable SDC-based workaround to achieves timing closure; adding create_generated_clock can lead to setup violations due to a zero clock relationship. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.Why does Nios® V/c processor fail to service interrupts when it is under CLINT-Vectored mode?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1, the Nios ® V/c processor might fail to service any interrupts when it is under CLINT-Vectored mode. The affected interrupts are platform interrupts, software interrupt, and timer interrupt. The following are not affected by this issue: Nios ® V/c processor under CLINT-Direct, Nios ® V/m processor, and Nios ® V/g processor This is because the Board Support Package Editor fails to generate relevant macros in system.h to support CLINT-Vectored mode. Resolution To continue using CLINT-Vectored with Nios ® V/c processor, add the following macros in the system.h. #define ALT_CPU_INT_MODE 1 #define NIOSVSMALLCORE_INT_MODE 1 #define INTEL_NIOSV_C_0_DM_AGENT_INT_MODE 1 This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software version 26.1.
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