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Question 1

7votes

1answer

418views

Button Debounce in Verilog

I'm learning FPGA development, and this is my first Verilog module - a button bouncer using a state machine. The code works as I expected it to be, but I would like some feedback on the code itself ...

Dang Quang Vinh

121

askedAug 14 at 5:41

Question 2

3votes

1answer

246views

Implements a READ ID command between the iCE40 HX8K and the AT25SF0818 in Verilog

QuestionHow can I improve my Verilog code?ContextFlash Read ID OperationThis project is an implimentation of theRead Manufacturer and Device ID (9Fh) operation ...

K_T

163

askedOct 12, 2024 at 10:03

Question 3

3votes

1answer

120views

SPI prototype in Verilog: areas for code improvement

I'm working on an SPI in Verilog. I will post what I came up with here. This is an educational project compiled according to the general principle from Wikipedia. There is only one mode - exchange ...

ayr

133

askedJul 9, 2024 at 3:32

Question 4

3votes

1answer

103views

Detect when X-axis inputs and Y-axis inputs go high

I am working on a module namedPinCoordinates that detects when X-axis and Y-axis inputs go high. This will be programmed onto an Altera MAX V CPLD. I am ...

Brandon Higgs-Carr

33

askedMar 25, 2024 at 20:12

Question 5

4votes

1answer

162views

Design and stimulus for a simple Mealy finite state machine

I am trying to code a state machine for the given state diagram:I...

Ervin Ranjan

43

askedNov 11, 2023 at 15:58

Question 6

1vote

1answer

134views

Clock frequency meter module

The module measures input clocks. It requires some reference clock. There can be from one to five input clocks to measure it. Output values are usual unsigned ones. As expected, it should be reset ...

Artem Shimko

35

askedAug 23, 2023 at 10:44

Question 7

5votes

1answer

742views

LED matrix controller - Verilog

I'm an ECE student. My experience in Verilog and FPGAs is mainly from my digital logic design class. To practice Verilog, I decided to implement a controller for Adafruit LED matrices. It interfaces ...

hjkl

143

askedAug 12, 2022 at 22:25

Question 8

1vote

1answer

193views

fixed pseudo-random binary sequence (prbs)

On recent comments based fixed modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by ...

Drakonof

453

askedDec 6, 2021 at 7:41

Question 9

4votes

1answer

375views

Heart beat RTL module

Heart rate or blink generator. Clocked from the system frequency, but calculated from a constant of 120MHz. Has a prescaler with values 2, 3, 5, 6, for even heart beat / blinking. The IS_DEBUG ...

Drakonof

453

askedDec 3, 2021 at 14:18

Question 10

2votes

1answer

2kviews

pseudo-random binary sequence (prbs)

Modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by transferring the bus to, for ...

Drakonof

453

askedNov 26, 2021 at 12:59

Question 11

3votes

1answer

2kviews

Carry Lookahead Adder - SystemVerilog

I have been learning SystemVerilog before I go back to school and decided to try and implement a Carry Lookahead Adder. As far as I can tell, it works correctly though I haven't tested extensively, ...

Carson

193

askedAug 6, 2021 at 6:46

Question 12

2votes

0answers

421views

a simple interrupt polling program due to AXI DMA IP

The program transfers a data array from a Zynq-7000 PS DDR to a BRAM IP (block RAM) memory in a PL part of a FPGA due to a PL AXI DMA IP. Inferring a xilinx axi dma driver (not scatter-gather mode), ...

Drakonof

453

askedFeb 25, 2021 at 11:48

Question 13

6votes

1answer

841views

VGA sync generator for 640x480@60Hz

I wrote my first module in Verilog. The purpose is to maintain two counters and emit signals corresponding to VGA's HSync and VSync, as well as HBlank and VBlank pulses to be used by a video ...

robbie

261

askedJul 12, 2019 at 3:14

Question 14

7votes

1answer

152views

Signal output on Raspberry Pi that acts as input for FPGA

ProblemI'm writing a verilog program that does the trapezoidal integration method (where a review is also welcome, wink wink). But turns out you need input for these kind of things, so in the overly ...

auden

441

askedAug 7, 2018 at 0:49

Question 15

6votes

2answers

1kviews

Verilog implementation of trapezoidal integration method

Any and all comments are welcome in this review.##ProblemI've been doing a lot with numerical integration methods recently and have mostly been programming in Python. But, speedups and FPGAs are ...

auden

441

askedJul 31, 2018 at 18:20

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Stack Exchange Network

Questions tagged [fpga]

Button Debounce in Verilog

Implements a READ ID command between the iCE40 HX8K and the AT25SF0818 in Verilog

SPI prototype in Verilog: areas for code improvement

Detect when X-axis inputs and Y-axis inputs go high

Design and stimulus for a simple Mealy finite state machine

Clock frequency meter module

LED matrix controller - Verilog

fixed pseudo-random binary sequence (prbs)

Heart beat RTL module

pseudo-random binary sequence (prbs)

Carry Lookahead Adder - SystemVerilog

a simple interrupt polling program due to AXI DMA IP

VGA sync generator for 640x480@60Hz

Signal output on Raspberry Pi that acts as input for FPGA

Verilog implementation of trapezoidal integration method

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