A capacitorless twin-transistor random access memory (TTRAM) on SOI

@article{Morishita2005ACT,  title={A capacitorless twin-transistor random access memory (TTRAM) on SOI},  author={Fukashi Morishita and Hideyuki Noda and Isamu Hayashi and Takayuki Gyohten and Mako Okamoto and Takashi Ipposhi and Shigeto Maegawa and Katsumi Dosaka and Kazutami Arimoto},  journal={Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.},  year={2005},  pages={435-438},  url={https://api.semanticscholar.org/CorpusID:14952912}}
The TTRAM cell has two data-storage states and the data retention time of 100ms at 80/spl deg/C is confirmed, and the process is compatible with the conventional SOI-CMOS and never requires any additional processes.

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