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AUCOHL /Fault

A complete open-source design-for-testing (DFT) Solution

testing dft eda verilog verilog-hdl jtag atpg fault-simulation vlsi-cad scan-chains stuck-at

UpdatedNov 2, 2024
Swift

PKU-IDEA /OpenPARF

🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit

UpdatedApr 25, 2025
C++

asyncvlsi /act

ACT hardware description language and core tools.

language eda circuit-simulator cad dataflow chp dataflow-programming prs hdl vlsi hardware-description-language production-rules design-automation asynchronous-circuits vlsi-cad asynchronous-vlsi communicating-hardware-processes

UpdatedApr 24, 2025
C++

ieee-ceda-datc /RDF-2019

DATC RDF

routing eda cad vlsi logic-synthesis placement vlsi-physical-design design-automation design-flow vlsi-cad ieee-ceda ieee-ceda-datc vlsi-design-flow clock-tree

UpdatedJul 31, 2020
Verilog

VLSI-Physical-Design-Automation

twweeb /VLSI-Physical-Design-Automation

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

eda vlsi nthu vlsi-physical-design vlsi-design vlsi-placement vlsi-cad physical-design-automation vlsi-floorplan vlsi-routing two-way-min-cut fixed-outline global-placement global-routing

UpdatedJan 23, 2021
C++

UdayaShankarS /TCL-Scripting

Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference

vlsi-physical-design tcl-scripts vlsi-cad

UpdatedDec 30, 2022
Tcl

paripath /cdf

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

characterization power-analysis hspice spice-simulator vlsi-circuits timing-analysis vlsi-design vlsi-cad

UpdatedFeb 13, 2020
C++

CaiB /GDStoSVG

Converts GDSII (IC layout database) files to SVG (Vector graphics) files.

svg converter vlsi vlsi-cad

UpdatedFeb 10, 2023
C#

HsuChiChen /ncku-intro-vlsi

grayscale conversion system and simple convolution system

convolutional-neural-networks hardware-acceleration hspice grayscale-image-converter vlsi-cad

UpdatedAug 25, 2021
Verilog

rohankalbag /vlsi-circuit-partitioning-algorithms

Course Project - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay

python algorithms networkx graph-theory clustering-algorithm kernighan-lin vlsi-cad circuit-partitioning eig-partitioning

UpdatedDec 9, 2022
Jupyter Notebook

Sooryakiran /Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

Domain Specific Hardware Accelerators - VLSI CAD Project

processor-architecture ram hardware processor bus bluespec hardware-designs vlsi hardware-acceleration vlsi-physical-design bluespec-systemverilog processor-design vector-processor vlsi-design bluespec-systemverilog-language vlsi-cad

UpdatedJan 11, 2021
Bluespec

karthik-r-rao /VLSI_Physical_Design_Tool

A simple tool to demonstrate the physical design steps of VLSI Design Flow.

vlsi vlsi-physical-design vlsi-design vlsi-project vlsi-cad

UpdatedDec 13, 2020
Python

A-Primer-For-Physical-Design-Automation

neeraj1397 /A-Primer-For-Physical-Design-Automation

This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.

algorithms eda python3 vlsi-physical-design vlsi-design asic-design vlsi-cad vlsi-pda

UpdatedMar 3, 2024
Jupyter Notebook

MayurTA /VSD-IAT_workshop

Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry

vsd vlsi vlsi-cad openlane gdsii-flow openlane-flow

UpdatedFeb 25, 2021

PKU-IDEA /OpenPARF-MLCAD2023

🕹 OpenPARF-MLCAD2023: A Multi-Electrostatics Based FPGA Macro Placer Considering Cascaded Macros Groups and Fence Regions (MLCAD'23 Contest Submission)

fpga mlcad vlsi-cad

UpdatedOct 8, 2024
C++

rohankalbag /optiVLSI

A library for fast and optimized VLSI Computer-Aided-Design algorithms

python graph-algorithms logic-simulator vlsi-cad binary-decision-diagram automan numba-jit

UpdatedMay 8, 2023
Python

RithikNambiar /vim_dotfiles

Contains vim dotfiles configured for verilog, C++ & some stuff for VLSI

vim vimrc vim-configs vim-plugin vim-configuration vim-plugins ide verilog vim-colorscheme sdc hdl vlsi verilog-hdl vimscript vlsi-physical-design upf vlsi-circuits verilog-project vlsi-design vlsi-cad

UpdatedAug 14, 2021
Vim Script

the-pinbo /ROBDD

A binary decision diagram is a directed acyclic graph used to represent a Boolean function. The ROBDD is a canonical form, which means that given an identical ordering of input variables, equivalent Boolean functions will always reduce to the same ROBDD.

bdd boolean-algebra vlsi graphviz-dot robdd bdds ipynb-jupyter-notebook pthon3 vlsi-cad

UpdatedOct 2, 2022
Jupyter Notebook

cuhk-eda /split-extract

Heterogeneous Feature Extraction for Split Manufactured Layouts with Routing Perturbation

deep-neural-networks manufacturing intellectual-property hardware-security electronic-design-automation vlsi-cad

UpdatedJan 30, 2021
C++

rohankalbag /logic-simulator

Course Assignment - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay

python netlist combinational-circuit logic-simulator vlsi-cad

UpdatedDec 10, 2022
Jupyter Notebook

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