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stuck-at

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A complete open-source design-for-testing (DFT) Solution

  • UpdatedNov 2, 2024
  • Swift

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

  • UpdatedNov 20, 2023
  • Verilog

Simple fault simulator

  • UpdatedJun 20, 2021
  • C

SPM with DFT structure automatically injected by Fault

  • UpdatedFeb 14, 2021
  • Verilog

This is a Combinational Circuit Logic Simulation Tool. There is a C++ version and a C version.

  • UpdatedMay 17, 2022
  • C++

Raspberry Pi 4 is used to drive ATPG stuck-at patterns to an IC. Python is used to drive the patterns and check for expected levels on the scan_out pins (4 chains in this example). A Perl script is used to parse the ATP pattern data into Python lists (I prefer to parse text files using Perl).

  • UpdatedOct 22, 2022
  • Python

Simple EDA tool for fault reduction and testing for combinational circuits

  • UpdatedJul 31, 2023
  • Python

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