netlist

A hand-drawn schematic sketch recognizer and converter. Traditional object detection techniques built using OpenCV; deep learning classification powered by TensorFlow 2 using the Keras API.

opencv computer-vision schematic circuits netlist electrical-engineering schematic-converter circuit-design offline-recognition

UpdatedFeb 20, 2025
Jupyter Notebook

najaeda /naja-verilog

Star37

A standalone structural (gate-level) verilog parser

parser cpp eda verilog netlist semiconductor netlist-parser electronic-design-automation

UpdatedJul 13, 2025
C++

jimwang99 /parser-for-chip-design

Star33

A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).

python verilog liberty netlist

UpdatedJun 13, 2015
Python

SpiceSharp /SpiceSharpParser

Star30

SPICE netlists parser for .NET

parser csharp dotnet electronics spice netlist

UpdatedJan 9, 2025
C#

arasgungore /netlist-solver

Star22

A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit.

algorithm algorithms matlab circuit-simulator circuits circuit circuit-simulation nodal-analysis circuit-analysis netlist mna circuits-simulator analog-design netlist-parser netlists circuit-theory modified-node-analysis modified-nodal-analysis node-analysis netlist-simulator

UpdatedAug 8, 2022
MATLAB

kailiuXD /xdcom

Star13

This is a demo for still image compression application

hardware-architectures verilog image-compression jpeg2000 netlist arithmetic-coding

UpdatedApr 14, 2018
Verilog

akashlevy /pyxbar

Star13

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

python generator simulation waveform nvm spice circuit testbench netlist hspice verilog-a rram memory-design

UpdatedJan 22, 2020
SourcePawn

ganeshgore /spydrnet-physical

Star13

This is a SpyDrNet Plugin for a physical design related transformations

automation verilog hdl netlist vlsi-physical-design spydrnet

UpdatedJun 13, 2025
Python

FPGAsm /FPGAsm

Star11

A low-level hierarchical netlist assembler for FPGAs

fpga netlist netlists hdls

UpdatedJul 26, 2021
C++

emsec /hal-benchmarks

Star11

Benchmark suite for HAL

hardware vhdl reverse-engineering verilog netlist

UpdatedNov 9, 2020
VHDL

byuccl /spydrnet-tmr

Star10

TMR utilities for the SpyDrNet project

fpga digital transformations verilog hardware-designs transformation netlist computer-aided-design fpgas electronic-design-automation tmr triple-modular-redundancy blif netlists edif spydrnet eblif

UpdatedNov 7, 2023
Python

SinaKarvandi /hardware-design-stack

Star9

The source codes used in the blog post available at:https://rayanfam.com/topics/hardware-design-stack/

asic fpga vhdl chisel chisel3 verilog vivado gtkwave modelsim netlist verilator vivado-hls asic-design vitis openram openlane vitis-hls

UpdatedOct 8, 2023
VHDL

jvestman /skimibowi

Star7

SKiDL Microcontroller Board Wizard

pyqt5 wizard kicad netlist microcontroller-boards netlists circuits-and-electronics

UpdatedSep 23, 2023
Python

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netlist

Here are 43 public repositories matching this topic...

nturley /netlistsvg

emsec /hal

google /pcbdl

circuitgraph /circuitgraph

najaeda /naja

byuccl /spydrnet

electron-lang /electron

aaanthonyyy /CircuitNet

najaeda /naja-verilog

jimwang99 /parser-for-chip-design

SpiceSharp /SpiceSharpParser

arasgungore /netlist-solver

kailiuXD /xdcom

akashlevy /pyxbar

ganeshgore /spydrnet-physical

FPGAsm /FPGAsm

emsec /hal-benchmarks

byuccl /spydrnet-tmr

SinaKarvandi /hardware-design-stack

jvestman /skimibowi

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