icarus-verilog

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olofk /edalize

Star683

An abstraction library for interfacing EDA tools

fpga simulation vhdl eda verilog xilinx synthesis vivado altera systemverilog icestorm lattice icarus-verilog modelsim ghdl yosys verilator riviera-pro fossi spyglass

UpdatedMay 2, 2025
Python

dpretet /async_fifo

Sponsor

Star330

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

UpdatedApr 30, 2024
Verilog

mshr-h /vscode-verilog-hdl-support

Sponsor

Star320

HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

UpdatedMay 2, 2025
TypeScript

scarv /xcrypto

Star92

XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

UpdatedJan 5, 2023
Verilog

stnolting /neorv32-verilog

Star81

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

asic fpga verilog icarus-verilog ghdl neorv32

UpdatedApr 28, 2025
VHDL

dpretet /svut

Sponsor

Star78

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

python flow simulator tdd simulation foss verilog testcase tdd-utilities mit-license systemverilog icarus-verilog gtkwave verification-methodologies vcd verilator surfer svut

UpdatedOct 22, 2024
Python

unixb0y /SystemVerilogSHA256

Star78

SHA256 in (System-) Verilog / Open Source FPGA Miner

fpga bitcoin mining verilog sha256 systemverilog icarus-verilog

UpdatedMar 10, 2018
SystemVerilog

sgherbst /svreal

Star44

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim

UpdatedJan 13, 2021
SystemVerilog

albertxie /iverilog-tutorial

Star39

Quickstart guide on Icarus Verilog.

verilog signal icarus-verilog gtkwave csc258

UpdatedJun 18, 2020
Verilog

yasnakateb /PipelinedARM

Star19

💎 A 32-bit ARM Processor Implementation in Verilog HDL

arm cpu verilog icarus-verilog verilog-hdl iverilog arm-processor arm-pipeline

UpdatedMar 21, 2022
Verilog

sifferman /fusesoc_template

Star17

Example of how to get started with olofk/fusesoc.

vivado icestorm icarus-verilog yosys fusesoc tinyfpga-bx nexys-a7 nextpnr-ice40

UpdatedJul 25, 2021
Python

aditeyabaral /DDCO-Lab-UE18CS207

Star16

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

verilog logic-programming icarus-verilog digital-design computer-organization verilog-code

UpdatedApr 17, 2020
Verilog

esynr3z /pyhdlsim

Star15

Example of Python and PyTest powered workflow for a HDL simulation

python asic fpga pytest rtl verilog icarus-verilog hdl modelsim system-verilog vivado-simulator

UpdatedJan 17, 2021
Python

Elphel /vdt-plugin

Star15

mirror ofhttps://git.elphel.com/Elphel/vdt-plugin

eclipse ide eclipse-plugin verilog vivado icarus-verilog gtkwave quartus cocotb

UpdatedNov 29, 2017
Java

addisonElliott /SCIC

Star14

Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.

asic cpu digital simulation tcl rtl verilog synthesis icarus-verilog gate cadence

UpdatedNov 29, 2018
Verilog

TheOneKevin /icarusext

Star11

iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.

verilog vscode-extension icarus-verilog gtkwave verilog-testbenches

UpdatedMar 4, 2023
TypeScript

yasnakateb /NoCRouter

Star11

👶🏻 My first baby steps into the world of NoC

router verilog icarus-verilog verilog-hdl iverilog

UpdatedSep 1, 2022
Verilog

SymbiFlow /XilinxUnisimLibrary

Star9

Apache 2.0 licensed copy of the Xilinx Unisim library.

simulation xilinx vivado icarus-verilog icarus verilator

UpdatedJul 22, 2020
Verilog

varkenvarken /robin

Star8

SoC design targeted at the IceBreaker board

cpu processor verilog robin icestorm alu icarus-verilog soc yosys icestick icebreaker next-npr

UpdatedMar 21, 2020
Assembly

FPGAwars /toolchain-iverilog

Star8

🌱 Icarus Verilog pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS

toolchain platformio icarus-verilog apio

UpdatedMay 9, 2022
Verilog

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icarus-verilog

Here are 75 public repositories matching this topic...

olofk /edalize

dpretet /async_fifo

mshr-h /vscode-verilog-hdl-support

scarv /xcrypto

stnolting /neorv32-verilog

dpretet /svut

unixb0y /SystemVerilogSHA256

sgherbst /svreal

albertxie /iverilog-tutorial

yasnakateb /PipelinedARM

sifferman /fusesoc_template

aditeyabaral /DDCO-Lab-UE18CS207

esynr3z /pyhdlsim

Elphel /vdt-plugin

addisonElliott /SCIC

TheOneKevin /icarusext

yasnakateb /NoCRouter

SymbiFlow /XilinxUnisimLibrary

varkenvarken /robin

FPGAwars /toolchain-iverilog

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