ddr

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA [FCCM 20]

benchmark fpga ddr hbm

UpdatedSep 15, 2023
SystemVerilog

splinedrive /my_hdmi_device

Star98

New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!

ddr verilog sdr hdmi dvi vga ice40 icestick icoboard pmod ecp5 ulx3s tmds blackicemx dvi-standard hdmi-device tmds-encoding arty7 sipeed-tang-nano sipeed-tang-nano4k

UpdatedOct 16, 2023
GLSL

adibis /DDR2_Controller

Star78

DDR2 memory controller written in Verilog

ddr verilog hdl verilog-project

UpdatedFeb 28, 2012
Verilog

3F /aml_s905_uboot

Star71

u-boot DDR mods ~

memory ddr amlogic u-boot s905 ddrpara mtool aml-encrypt-gxb

UpdatedJul 18, 2021
C

Liu-Cheng /cycle-accurate-SystemC-simulator-over-ramulator

Star50

An example of using Ramulator as memory model in a cycle-accurate SystemC Design

accelerator ddr cycle-accurate systemc ramulator

UpdatedJun 30, 2017
C++

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

opensource video fpga camera serdes ddr raspberrypi rtl isp vlc hdmi systemverilog csi hd image-sensor uhd low-budget imx283 signal-integrity

UpdatedMay 14, 2025
SystemVerilog

Elphel /eddr3

Star40

mirror ofhttps://git.elphel.com/Elphel/eddr3

fpga zynq ddr verilog xilinx open-core ddr3 memory-controller

UpdatedOct 16, 2017
Verilog

d953i /Custom_Part_Data_Files

Star38

Xilinx PCIe to MIG DDR4 example designs and custom part data files

csv fpga ddr tcl calibration verilog xilinx vivado mig axi sqrl ddr4 vcu1525 bcu1525 dimm udimm rdimm sodimm

UpdatedFeb 4, 2024
Tcl

hellojavaer /ddal

Star34

DDAL(Distributed Data Access Layer) is a simple solution to access database shard.

mysql converter schema sql ddr transaction shard load-balancer distributed sequence datasource access-database-shard

UpdatedJun 15, 2018
Java

mizztgc /konaste-linux

Star24

Unofficial script for playing KONAMI Amusement Game Station (Konaste/コナステ) games on Linux (and possibly other *nix OSes), using Wine

soundvoltex sdvx ddr dancedancerevolution popn iidx konami beatmania beatmania-iidx bemani popnmusic gitadora infinitas konaste bombergirl iidx-infinitas bomber-girl

UpdatedApr 20, 2025
Shell

city41 /stepcharts

Star23

A modern website for DDR stepcharts. Think of them like guitar tabs, but for the songs's dance steps in the game.

react website gaming ddr rhythm-game

UpdatedAug 23, 2024
TypeScript

zslwyuan /Zynq_HLS_DDR_Dataflow_kernel_2mm

Star21

This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation

tutorial zynq hls ddr matrix-multiplication vivado zynq-7000