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pulp-platform /axi

Star1.3k

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

UpdatedJul 10, 2025
SystemVerilog

taichi-ishitani /tvip-axi

Sponsor

Star410

AMBA AXI VIP

vip systemverilog uvm axi amba axi4 amba-axi

UpdatedJun 28, 2024
SystemVerilog

rggen /rggen

Star404

Code generation tool for control and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents

UpdatedJun 1, 2025
Ruby

ZipCPU /sdspi

Star301

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface

UpdatedApr 24, 2025
Verilog

taichi-ishitani /tnoc

Sponsor

Star184

Network on Chip Implementation written in SytemVerilog

systemverilog uvm noc axi amba network-on-chip axi4 amba-axi

UpdatedAug 27, 2022
SystemVerilog

hdl-modules /hdl-modules

Star172

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

asic fpga hardware amd vhdl intel eda rtl ip xilinx vivado altera fifo cdc axi microsemi clock-domain-crossing asynchronous-fifo axi-lite efinix

UpdatedJun 27, 2025
VHDL

SystemRDL /PeakRDL

Star138

Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

UpdatedMay 23, 2025
Python

lucky-wfw /ARM_AMBA_Design

Star127

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

arm verilog axi amba apb ahb

UpdatedMay 14, 2021
Verilog

hdl-registers /hdl-registers

Star71

An open-source HDL register code generator fast enough to run in real time.

python c html asic generator fpga cplusplus register vhdl eda rtl csr axi axi-lite register-interface

UpdatedJun 23, 2025
Python

pulp-platform /axi_mem_if

Star42

Simple single-port AXI memory interface

asic fpga axi systemverilog-hdl

UpdatedJun 7, 2024
SystemVerilog

esynr3z /axi_vip_demo

Star41

Xilinx AXI VIP example of use

fpga xilinx systemverilog axi

UpdatedApr 24, 2021
SystemVerilog

RSPwFPGAs /opae-xilinx

Star39

OPAE porting to Xilinx FPGA devices.

fpga xilinx pcie fpga-accelerator axi partial-reconfiguration opae platform-reuse

UpdatedAug 5, 2020
Coq

d953i /Custom_Part_Data_Files

Star38

Xilinx PCIe to MIG DDR4 example designs and custom part data files

csv fpga ddr tcl calibration verilog xilinx vivado mig axi sqrl ddr4 vcu1525 bcu1525 dimm udimm rdimm sodimm

UpdatedFeb 4, 2024
Tcl

wyvernSemi /mem_model

Star24

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

simulation vhdl verilog questasim ghdl avalon memory-model test-bench pli verilog-components verilator axi nvc dpi-c cosimulation vivado-simulator verilog-testbenches

UpdatedJul 8, 2025
VHDL

Wissance /QuickSPI

Star22

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

spi-interface fpga spi altera verilog-hdl xilinx-fpga xilinx-vivado verilog-components axi verilog-snippets spi-hdl spi-ip-core spi-pld spi-fpga verilog-spi axi-interfaces bit-oriented-spi soft-spi hard-spi dragster-spi

UpdatedNov 21, 2017
Verilog

hplp /aes_chisel

Star20

Implementation of the Advanced Encryption Standard in Chisel

aes chisel firrtl verilog avalon axi advanced-encryption-standard parameterized rocc

UpdatedApr 18, 2022
Scala

pulp-platform /axi_node

Star19

AXI X-Bar

asic fpga systemverilog axi

UpdatedApr 8, 2020
SystemVerilog

atfox272 /AXI4-Interconnect

Star18

RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.

axi interconnect axi4

UpdatedMar 13, 2025
Verilog

mwrnd /innova2_xcku15p_ddr4_bram_gpio

Star18

XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA

fpga vivado pcie axi ddr4 xdma innova2 xcku15p mnv303212a innova-2-flex mnv303212a-adlt 4xc7a16683 01pg974 pcie-xdma

UpdatedMar 7, 2024
Tcl

bselimoglu /SoC-ZedBoard-Zynq-7000-Labs

Star14

Hardware and Software Co-design implementations

sdk gpio fsm ddr zedboard dma bram axi zynq-7000 vivado-ip-integrator arm-cortex-a9 zynq7-ps high-performance-port

UpdatedDec 5, 2019

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