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AddBitPack
instance forIndex 0
#2784
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Review together with@DigitalBrains1
Nice, this would get rid of a lot of unwanted1 <= n
constraints.
Addthis fact to the typelits plugins.
I doubt reasoning about type families is in-scope for the plugins, but you might want to take that up with the maintainers :-).
I think we should change the cover letter's motivation to be something along the lines of "this aligns clash-the-compiler's thoughts onIndex 0
withBitPack (Index 0)
".
A changelog is needed, but that's also in the TODOs.
Other than that LGTUs.
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DigitalBrains1 commentedAug 8, 2024 • edited
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edited
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It seems to still need something more though:
Full message
Experienced with GHC 9.6.6. [edit] |
It's because of the new |
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CompareI understand the desire to get rid of that But lets say someone is (accidentally) calling |
I don't think that this is the right way to look at it. Consider the following example: topEntity::HiddenClockResetEnableSystem=>SignalSystem (Index0)topEntity=pure$ unpack@(Index0)$ resize (0::BitVector1) If that description is turned into Verilog with I agree that the user might end up with a run time error in simulation, if trying to inspect what comes out of applying Note that the type system never was intended to prevent us from this, in the same way as it cannot prevent us from ever having a look at the contents of |
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This PR gets rid of the additional
1 <= n
constraint for theBitPack
instance ofIndex n
.Background:
Index 0
andVoid
are empty types → isomorphic to the empty setIndex 1
and()
are singleton types → isomorphic to a singleton setHence, we only need to question ourselves: how many bits do you need to distinguish between different elements of these types / sets? In both cases the answer clearly is: 0. Thus,
BitSize (Index 0) = 0
.From another perspective: Clash generates valid HDL for
Index 0
and the number of bits required by the generated HDL is zero as well. Hence, there is no reason to hide this fact in the type system for this particular case.Still TODO: