VHDL-AMS is a derivative of thehardware description languageVHDL (IEEE 1076-2002). It includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems (IEEE 1076.1-2017).
The VHDL-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components.[1]
VHDL-AMS is an industry standard modeling language for mixed signal circuits. It provides both continuous-time and event-driven modeling semantics, and so is suitable for analog, digital, and mixed analog/digital circuits. It is particularly well suited for verification of very complex analog, mixed-signal andradio frequency integrated circuits.
In VHDL-AMS, a design consists at a minimum of anentity which describes the interface and anarchitecture which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures andconfigurations.
A simple idealdiode in VHDL-AMS would look something like this:
libraryIEEE;useIEEE.math_real.all;useIEEE.electrical_systems.all;-- this is the entityentityDIODEisgeneric(iss:current:=1.0e-14);port(terminalanode,cathode:electrical);endentityDIODE;architectureIDEALofDIODEisquantityvacrossithroughanodetocathode;constantvt:voltage:=0.0258;begini==iss*(exp(v/vt)-1.0);endarchitectureIDEAL;