MMX is asingle instruction, multiple data (SIMD)instruction set architecture designed byIntel, introduced on January 8, 1997[1][2] with itsPentiumP5 (microarchitecture) based line ofmicroprocessors, named "Pentium with MMX Technology".[3] It developed out of a similar unit introduced on theIntel i860,[4] and earlier theIntel i750 video pixel processor. MMX is aprocessor supplementary capability that is supported onIA-32 processors by Intel and other vendors as of 1997[update]. AMD also added MMX instruction set in itsK6 processor.
The New York Times described the initial push, includingSuper Bowl advertisements, as focused on "a new generation of glitzy multimedia products, including videophones and 3-D video games."[5]
MMX has subsequently been extended by several programs by Intel and others:3DNow!,Streaming SIMD Extensions (SSE), and ongoing revisions ofAdvanced Vector Extensions (AVX).
MMX is officially a meaninglessinitialism[6]trademarked by Intel;[7] unofficially, the initials have been variously explained as standing for
Advanced Micro Devices (AMD), during one of its many court battles with Intel, produced marketing material from Intel indicating that MMX stood for "Matrix Math Extensions".[citation needed] Since aninitialism cannot be trademarked,[citation needed] this was an attempt to invalidate Intel's trademark. In 1995, Intel filed suit against AMD and Cyrix Corp. for misuse of its trademark MMX. AMD and Intel settled, with AMD acknowledging MMX as a trademark owned by Intel, and with Intel granting AMD rights to use the MMX trademark as a technology name, but not a processor name.[9] Also the "MMX" term is sometimes confused with the separateMultiMedia Extensions API onWindows 3.x andWindows 9x.
MMX defines eightprocessor registers, named MM0 through MM7, and operations that operate on them. Each register is 64 bits wide and can be used to hold either 64-bitintegers, or multiple smaller integers in a "packed" format: one instruction can then be applied to two 32-bit integers, four 16-bit integers, or eight 8-bit integers at once.[10]
MMX provides only integer operations. When originally developed, for theIntel i860, the use of integer math made sense (both 2D and 3D calculations required it), but as graphics cards that did much of this became common, integerSIMD in the CPU became somewhat redundant for graphical applications.[citation needed] Alternatively, thesaturation arithmetic operations in MMX could[vague] significantly speed up somedigital signal processing applications.[citation needed]
To avoid compatibility problems with thecontext switch mechanisms in existing operating systems, the MMX registers are aliases for the existingx87floating-point unit (FPU) registers, which context switches would already save and restore. Unlike the x87 registers, which behave like astack, the MMX registers are each directly addressable (random access).
Any operation involving the floating-point stack might also affect the MMX registers and vice versa, so this aliasing makes it difficult to work with floating-point and SIMD operations in the same program.[11] To maximize performance, software often used the processor exclusively in one mode or the other, deferring the relatively slow switch between them as long as possible.
Each 64-bit MMX register corresponds to themantissa part of an 80-bit x87 register. The upper 16 bits of the x87 registers thus go unused in MMX, and these bits are all set to ones, making themNot a Number (NaN) data types, or infinities in the floating-point representation. This can be used by software to decide whether a given register's content is intended as floating-point or SIMD data.
Software support for MMX developed slowly.[5]Intel's C Compiler and related development tools obtainedintrinsics for invoking MMX instructions and Intel releasedlibraries of common vectorized algorithms using MMX. Both Intel andMetrowerks attemptedautomatic vectorization in their compilers, but the operations in theC programming language mapped poorly onto the MMX instruction set and custom algorithms as of 2000 typically still had to be written inassembly language.[11]
AMD, a competingx86 microprocessor vendor, enhanced Intel's MMX with their own3DNow! instruction set. 3DNow is best known for adding single-precision (32-bit) floating-point support to the SIMD instruction-set, among other integer and more general enhancements.
Following MMX, Intel's next major x86 extension was theStreaming SIMD Extensions (SSE), introduced with thePentium III family[12] in 1999,[13] roughly a year after AMD's 3DNow! was introduced.
SSE addressed the core shortcomings of MMX (inability to mix integer-SIMD ops with any floating-point ops) by creating a new 128-bit wide register file (XMM0–XMM7) and new SIMD instructions for it. Like 3DNow!, SSE focused exclusively on single-precision floating-point operations (32-bit); integer SIMD operations were still performed using the MMX register and instruction set. However, the new XMM register-file allowed SSE SIMD-operations to be freely mixed with either MMX or x87 FPU ops.
Streaming SIMD Extensions 2 (SSE2), introduced with thePentium 4, further extended the x86 SIMD instruction set with integer (8/16/32 bit) and double-precision floating-point data support for the XMM register file. SSE2 also allowed the MMXoperation codes (opcodes) to use XMM register operands, extended to even wider YMM and ZMM registers by later SSE revisions.
Intel's andMarvell Technology Group'sXScale microprocessor core starting with PXA270 include anSIMDinstruction set architecture extension to theARM architecture core namedIntel Wireless MMX Technology (iwMMXt) which functions are similar to those of theIA-32 MMX extension.[14][15][16] It provides arithmetic and logic operations on 64-bit integer numbers, in which the software may choose to instead perform two 32-bit, four 16-bit or eight 8-bit operations in one instruction. The extension contains 16 data registers of 64-bits and eight control registers of 32-bits. All registers are accessed through standard ARM architecture coprocessor mapping mechanism. iwMMXt occupies coprocessors 0 and 1 space, and some of its opcodes clash with the opcodes of the earlier floating-point extension, FPA.[citation needed]
Later versions of Marvell's ARM processors support bothWireless MMX (WMMX) andWireless MMX2 (WMMX2) opcodes.
Intel's new multimedia extension technology, called MMX, ...
the name, which doesn't stand for anything
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