Movatterモバイル変換

Barrel processor

From Wikipedia, the free encyclopedia

CPU that switches between threads of execution on every cycle

Abarrel processor is aCPU that switches betweenthreads of execution on everycycle. ThisCPU design technique is also known as "interleaved" or "fine-grained"temporal multithreading. Unlikesimultaneous multithreading in modernsuperscalar architectures, it generally does not allow execution of multiple instructions in one cycle.

Likepreemptive multitasking, each thread of execution is assigned its ownprogram counter and otherhardware registers (each thread'sarchitectural state). A barrel processor can guarantee that each thread will execute one instruction everyn cycles, unlike apreemptive multitasking machine, that typically runs one thread of execution for tens of millions of cycles, while all other threads wait their turn.

A technique calledC-slowing can automatically generate a corresponding barrel processor design from a single-tasking processor design. Ann-way barrel processor generated this way acts much liken separatemultiprocessing copies of the original single-tasking processor, each one running at roughly 1/n the original speed.^{[citation needed]}

History

[edit]

One of the earliest examples of a barrel processor was the I/O processing system in theCDC 6000 series supercomputers. These executed oneinstruction (or a portion of an instruction) from each of 10 different virtual processors (called peripheral processors or PPs) before returning to the first processor.^[1] FromCDC 6000 series we read that "The peripheral processors are collectively implemented as a barrel processor. Each executes routines independently of the others. They are a loose predecessor of bus mastering ordirect memory access."

One motivation for barrel processors was to reduce hardware costs. In the case of the CDC 6x00 PPUs, the digital logic of the processor was much faster than the core memory, so rather than having ten separate processors, there are ten separate core memory units for the PPUs, but they all share the single set of processor logic.

Another example is theHoneywell 800, which had 8 groups of registers, allowing up to 8 concurrent programs. After each instruction, the processor would (in most cases) switch to the next active program in sequence.^[2]

Barrel processors have also been used as large-scale central processors. TheTera MTA (1988) was a large-scale barrel processor design with 128 threads per core.^[3]^[4] The MTA architecture has seen continued development in successive products, such as theCray Urika-GD, originally introduced in 2012 (as the YarcData uRiKA) and targeted at data-mining applications.^[5]

Barrel processors are also found in embedded systems, where they are particularly useful for their deterministicreal-time thread performance.

An early example is the “Dual CPU” version of thefour-bit COP400 that was introduced byNational Semiconductor in 1981. This single-chipmicrocontroller contains two ostensibly independent CPUs that share instructions, memory, and most IO devices. In reality, the dual CPUs are a single two-thread barrel processor. It works by duplicating certain sections of the processor—those that store thearchitectural state—but not duplicating the main execution resources such asALU, buses, and memory. Separate architectural states are established with duplicated A (accumulators), B (pointer registers), C (carry flags), N (stack pointers), and PC (program counters).^[6]

Another example is theXMOS XCore XS1 (2007), a four-stage barrel processor with eight threads per core. (Newer processors fromXMOS also have the same type of architecture.) The XS1 is found in Ethernet, USB, audio, and control devices, and other applications where I/O performance is critical. When the XS1 is programmed in the 'XC' language, software controlleddirect memory access may be implemented.

Barrel processors have also been used in specialized devices such as the eight-threadUbicom IP3023 network I/O processor (2004).Some 8-bit microcontrollers byPadauk Technology feature barrel processors with up to 8 threads per core.

Comparison with single-threaded processors

[edit]

Advantages

[edit]

A single-tasking processor spends a lot of time idle, not doing anything useful whenever acache miss orpipeline stall occurs. Advantages to employing barrel processors over single-tasking processors include:

The ability to do useful work on the other threads while the stalled thread is waiting.
Designing ann-way barrel processor with ann-deeppipeline is much simpler than designing a single-tasking processor because a barrel processor never has apipeline stall and doesn't needfeed-forward circuits.
Forreal-time applications, a barrel processor can guarantee that a "real-time" thread can execute with precise timing, no matter what happens to the other threads, even if some other threadlocks up in aninfinite loop or is continuously interrupted byhardware interrupts.

Disadvantages

[edit]

There are a few disadvantages to barrel processors.

The state of each thread must be kept on-chip, typically in registers, to avoid costly off-chip context switches. This requires a large number of registers compared to typical processors.
Either all threads must share the samecache, which slows overall system performance, or there must be one unit of cache for each execution thread, which can significantly increase thetransistor count and thus the cost of such a CPU. However, inhard real-time embedded systems where barrel processors are often found, memory access costs are typically calculated assuming worst-case cache behavior, so this is a minor concern.^{[citation needed]} Some barrel processors such as theXMOS XS1 do not have a cache at all.