logic cell

logic cell

n
(Electronics) a logic circuit forming part of a chip
Collins English Dictionary – Complete and Unabridged, 12th Edition 2014 © HarperCollins Publishers 1991, 1994, 1998, 2000, 2003, 2006, 2007, 2009, 2011, 2014


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References in periodicals archive?
Sueyoshi, "COGRE: a configuration memory reduced reconfigurablelogic cell architecture for area minimization," Field Programmable Logic and Applications (FPL), pp.
In combination with the new high-current I/Os (100 mA) and the proven ConfigurableLogic Cell (CLC) along with I2C[TM], SPI and EUSART for communications, this integration helps speed design, eases implementation and adds flexibility.
In this adder, the AND-OR-Invertlogic cell has more NMOS transistor stacking than the existing full adder architecture cells.
Topics include the electrical behavior of a GOS fault affected dominologic cell, static code analysis of functional descriptions in SystemC, a reconfigurable embedded decompressor for test compression, and distributed wireless optical communications for humanitarian assistance in disasters.
The power switch is switched on and off by using control logic and is presented in thelogic cell as a standard.
This much-anticipated addition to Aldec's popular family of embedded development kits showcases at Embedded World on booth 4-560 in Hall 4, features a Xilinx Zynq UltraScale+ ZU19EG FFVB1517 MPSoC, which has more than 1 millionlogic cells, and a quad-core ARM[R] Cortex-A53 platform running at up to 1.5GHz.
Nouta, "VHDL Power estimation of CMOSLogic Cells", Proceedings - ProRISC CSSP97, Workshop on Circuits, Systems and Signal Processing, Mierlo, the Netherlands, November 27 - 28, 1997
Logic cells 314.880 Slices 49.200 Configurable logic blocks (CLBs) Max distributed 5.090 RAM (Kb) DSP48E1 slices 1.344 Interface blocks for PCI express 2 Total I/O banks 18 Max user I/O 720 Total number of configuration bits 104,465,888 Price $667.29 Table 9: FPGA circuit device utilization.
In [5, 6], the high threshold IG FinFETs were used as basiclogic cells to design circuits and the optimization procedure was not mentioned.
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