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Review ofInstruction Fetch

Wehave discussed the common fetch sequence in previous lectures.

Wehave given both the sequence of microoperations and the corresponding sequenceof control signals. Remember that memorytimings restrict access to memory during the
(Fetch, T1) time slot, so we elect to update the Program Counter during thistime.

Fetch,T0:      (PC)® B1,tra1,B3® MAR, READ.

Fetch,T1:      (PC)® B1, 1® B2,add,B3® PC.

Fetch,T2:      (MBR)® B2,tra2,B3® IR.

This lecture focuses on theimpact of incrementing the program counter on

       1)    the design of the ALU, and

       2)    the bus structure of the CPU.

Itis immediately obvious that the ALU must have either an addition operation oran increment (add 1) operation. Forsimplicity, the design uses a simple addition operation, associated with thecontrol signal“add”.

Wehave always assumed that the CPU has three internal data busses.

We now show why such aconfiguration is desirable.

ConstraintsDue to the ALU

Recallthat the ALU itself has two inputs and one output.

Weconsider how to create a bus structure for the CPU that will make efficient
use of this ALU. For this discussion, wefocus on the addition operation
associated with updating the PC (Program Counter).

One–BusDesign for the CPU

Thesimplest design for the CPU calls for one common internal bus.

Therestriction that only one binary data set can be on a single bus at
any given time gives rise to severe timing problems.

Specifically,it will take two clock pulses to put the two arguments (PC and 1)
on the bus and one clock pulse to transfer the updated value to the PC.

Thisone–bus design calls for two holding registers, here called “Y” and “Z”.

The control signals required for this structure are:

T1: 1® Bus, Bus® Y.

T2: PC® Bus, add.

T3: Z® Bus, Bus® PC.

Theaddition takes three clock pulses.

Itis easy to show that a 2–bus design requires
two clock pulses to perform the addition.

EfficientAddition Requires a Three–Bus Structure

Withthis structure, the CPU can complete the addition in one clock cycle.

Thisexample is only one case in which the CPU design is considerably simplified
by having a three bus structure.

It can be seen that havingthree internal busses only modestly increases the design
complexity of the CPU. This is considereda good trade–off.

ImmediateImplications of the Three–Bus Design

Thedesign of the CPU calls for it to have three internal busses.

Theseare called B1, B2, and B3.

B1and B2 serve as input busses for the ALU.

B3serves as an output bus for the ALU.

This design can be seenin another light.

B1and B2 are the only busses to which any register can transfer data directly.

B3is the only bus that can transfer data directly to any register.

The protocol forregister–to–register transfer becomes as follows:

1.    Transfer from the source register to eitherbus B1 or bus B2 (but not both).

2.    Signal the ALU to connect the appropriateinput bus to bus B3.

3.    Transfer the contents of bus B3 to thedestination register.

Thisimplies two additional ALU control signals:tra1and tra2

       tra1        transferthe contents of B1 to B3

       tra2        transferthe contents of B2 to B3

MoreRequirements of the Common Fetch Sequence

Let’s repeat the common fetchsequence and examine it for more requirements.

Fetch, T0:      (PC)® B1,tra1,B3® MAR, READ.

Fetch, T1:      (PC)® B1, 1® B2,add,B3® PC.

Fetch,T2:      (MBR)® B2,tra2,B3® IR.

T0: We have handled the requirements for bustransfer. This demands the signal
       tra1 to the ALU. The READcontrol signal goes to the memory interface.

T1: We have handled these requirements completely.

T2: Here we have two more registers to be assignedto input busses.
       My earlier designs required thatthe Memory Buffer Register and Instruction
       Register be assigned to differentbusses, so this design reflects that.

Connectingthe IR to Bus B1

Thestructure of the IR (Instruction Register) calls for bits to be sent directlyto the Control Unit and bits to be sent to the bus B1.

Wefocus on the twenty lower order bits of the IR: IR₁₉ – IR₀.

Insome instructions these bits IR₁₉ – IR₀ form an addressfor accessing memory.

Insome instructions these bits IR₁₉ – IR₀ are interpretedas an immediate operand,
       either a 20–bit (five hexadecimaldigit) bit mask,
       or a 20–bit two’s–complementsigned integer.

Insome instructions,     bits IR₁₉– IR₁₇ are part of the instruction and
                                       bitsIR₁₆ – IR₀ are not used.

Inany case, provision is made to transfer only bits IR₁₉ – IR₀to bus B1.

Thistransfer is enabled by the signal IR® B1.

SignExtension in Connecting the IR to Bus B1

Twoof the immediate instructions, LDI and ADDI, require the contents of bits IR₁₉– IR₀ to be sign extended and treated as a 32–bit two’s–complementinteger.

Theother instructions that use bits IR₁₉ – IR₀ treat them asan unsigned integer.

Tohandle this we have a control signal“Extend”,which is emitted by the control unit.

Hereis a representation of the transfer mechanism for the IR.

LabelingControl Signals

Controlsignals are Boolean signals with two values:

       Logic 1   Usuallyasserted as + 5 volts.

       Logic 0   Usually asserted as 0 volts.

Eachcontrol signal is labeled by the action that it enables.

       IR® B1        Thissignal enables the transfer of IR₁₉ – IR₀ to bus B1.
                               It mightbe called IR_19–0® B1

       Extend            WhenIR® B1 is asserted, thiscauses the transfer to
                               be signextended.

Controlsignals that enable data transfers to either bus B1 or bus B2 will take
effect by enabling a tri–state buffer. The IR is one of many possible inputs to B1.

The CompleteConnection Scheme for the Instruction Register

Hereis a schematic that shows the basic processes associated with the transfer.

TheControl Unit emits both signals (Extend and IR® B1). Only thelatter is shown explicitly, due to a desire to keep the figure uncluttered.

The GeneralPurpose Registers

Inthis version of the design, the CPU has eight general–purpose registers.

       R0          Thisregister is read–only, holding the value 0.

       R1 – R7  These seven registers are read/write and can be used for anypurpose.
                       They are oftenused as index registers.

Eachof these eight registers can output to either bus B1 or bus B2.

BusB3 can place data into any of the seven registers R1 – R7, but is not connectedto R0.

The CompleteRegister Set

Hereis the complete register set and bus structure for the CPU. Note the two special purpose constantregisters +1 and –1, used by the Control Unit.

Attachingthe General Purpose Registers to the Bus Structure

Thereare only three control signals emitted by the Control Unit that enable thesetransfers. These are:

       R® B1          The selected register is copied to bus B1.

       R® B2          The selected register is copied to bus B2.

       B3® R          The contents of bus B3 are copied into the selectedregister.

Wenow ask how each of these registers is selected.

TheControl Unit uses three selector registers, each based on bit fields in the IR.
The generation of these selector registers will be discussed later.

       B1S        Thisselects the register to be placed on B1 when R® B1 is asserted.

       B2S        Thisselects the register to be placed on B2 when R® B2 is asserted.

       B3D        Thisselects the register to copy the contents of B3
                       when B3® R is asserted. If B3D = 000, no transfer occurs.

Eachof the signals B1S and B2S is the control input to an 8–to–1 multiplexer thatoutputs to a bus through a tri–state buffer enabled by the appropriate controlsignal.

The signal B3D is the 3–bitinput to an active–high 3–to–8 decoder that is
enabled by the control signal B3® R.

Figure:Connecting a Single Bit to the Busses

Comments onthe Connection

Transfer to a register.

Whencontrol signal B3® R is asserted, the 3–to–8 decoder is activated and asserts the clockinput of all flip–flops associated with the selected register.

Eachflip–flop associated with the selected register takes input from its bit lineon B3.

Output0 of the decoder is not connected to any register, so that asserting
B3® R when B3D = 000 has noeffect.

IfB3® R is not asserted, alldecoder outputs are 0 and nothing happens.

Transfer from a register.

Notethat the selector registers B1S and B2S always have values, so that the outputof the multiplexer associated with each bus always copies some general–purposeregister.

Whencontrol signal R® B1 is asserted the selected register is output to bus B1.
If it is not asserted, either B1 is not active or a special purpose register isfeeding it.

Whencontrol signal R® B2 is asserted the selected register is output to bus B2.
If it is not asserted, either B2 is not active or a special purpose register isfeeding it.

Itis expected that the two signals R® B1 and R® B2 can be asserted simultaneously.