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Chapter 10 –Overview of Busses

This chaptercontains some important material that is often overlooked in textbooks; indeed,it
has been overlooked in every previous edition of this textbook. Computer busses form the
topic of this chapter, which shall focus on issues common to the design of alldata busses while
mentioning specific data bus types as illustrations. Other chapters, specifically those on
memory, the CPU, and the I/O system will discuss the details of a bus as itapplies to each of
those design areas. The reader shouldnote that this chapter will contain some material that is
duplicative of that found in the other chapters; this is intentional.

A typicalcomputer contains a number of busses, at various levels. As we shall see in a later chapter, the CPU(Central Processing Unit) contains internal busses that are used to connect theALU (Arithmetic Logic Unit) with the register file, as well as with otherinternal registers. This chapter willfocus on the other busses in the computer, as they present design issues notseen in the CPU internal busses. Thetop–level logical architecture is as follows.

As noted above,the topics for this chapter focus on those busses that are outside of theCPU. As we shall see, some earlydesigns, such as the PDP–11 from the 1970’s, had only one bus external to theCPU. We shall see the bus structureevolve in response to commercial pressures.

RealityIntrudes

The design on the previous slide is logically correct, butit no longer represents the actual organization of any modern commercialcomputers. The problem is that the buscannot handle the work load associated with modern computers, especially therequirement for fast access to memory and intense data rates to the graphicscard.

Here is a refinement of the above diagram. We now have two fast busses, one each for thegraphics card and the memory. I/Odevices are relegated to the system bus.

This design is getting closer toreality. 

We now turn to commercial realities, specificallylegacy I/O devices. When upgrading a computer, most users do notwant to buy all new I/O devices (expensive) to replace older devices that stillfunction well. The I/O system mustprovide a number of busses of different speeds, addressing capabilities, anddata widths, to accommodate this variety of I/O devices.

Here we show the main I/O bus connecting the CPU to theI/O Control Hub (ICH), which isconnected to two I/O busses:one forslower (older) devices
                                              one for faster (newer)devices.

The requirement to handle memory aswell as a proliferation of I/O devices has lead to a new design based on twocontroller hubs:

           1.        The Memory Controller Hub or “NorthBridge”

           2.        The I/O Controller Hub or “SouthBridge”

Such a design allows for grouping the higher–data–rateconnections on the faster controller, which is closer to the CPU, and groupingthe slower data connections on the slower controller, which is more removedfrom the CPU. The names “Northbridge”and “Southbridge” come from analogy to the way a map is presented. In almost all chipset descriptions, theNorthbridge is shown above the Southbridge. In almost all maps, north is “up”.

It is worth note that, in later designs, much of thefunctionality of the Northbridge has been moved to the CPU chip.

BackwardCompatibility in System Buses

The early evolution of the Intel microcomputer line providesan interesting case study in the effect of commercial pressures on system busdesign. We focus on three of theearliest models, the Intel 8086, Intel 80286, and Intel 80386. All three had 16–bit data lines.
           The Intel 8086 had a 20–bitaddress line. It could address 1 MB ofmemory.
           The Intel 80286 had a 24–bitaddress line. It could address 16 MB ofmemory.
           The Intel 80386 had a 32–bitaddress line. It could address 4 GB ofmemory.

Here is a figure showing the growth of the address busstructure for these three designs. Notethat an old style (Intel 8086) bus interface card could be inserted into the20–bit slot of either the Intel 80286 or Intel 80386, and still functionnormally. The Intel 80286 interface,with its 24 bits of address split into two parts, could fit the 24–bit (20 bitsand 4 bits) slot of the Intel 80386.

The Intel 80286 was marketed as the IBM PC/AT (AdvancedTechnology). Your author fondlyremembers his PC/AT from about 1986; it was his first computer with a hard disk(40 MB).

Detour:The IBM Micro–Channel Bus

The Micro–Channel Architecture was a proprietary bus createdby IBM in the 1980’s for use on their new PS/2 computers. It was first introduced in 1987, but neverbecame popular. Later, IBM redesignedmost of these systems to use the PCI bus design (more on this later). The PS/2 line was seen by IBM as a follow–onto their PC/AT line, but was always too costly, typically selling at apremium. In 1990, the author of thistextbook was authorized to purchase a new 80386–class computer for hisoffice. The choice was either an IBM MCAunit or a PC clone. This was put out for bids. When the bids were received, the lowest IBM price was over $5,000, whilea compatible PC of the same power was $2,900.

According to Wikipedia 

“Although MCA was a huge technical improvement over ISA, its introductionand marketing by IBM was poorly handled. IBM did not develop a peripheral cardmarket for MCA, as it had done for the PC. It did not offer a number ofperipheral cards that utilized the advanced bus-mastering and I/O processingcapabilities of MCA. Absent a pattern, few peripheral card manufacturersdeveloped such designs on their own. Consequently customers were not providedmany advanced capabilities to justify the purchase of comparatively moreexpensive MCA systems and opted for the plurality of cheaper ISA designsoffered by IBM's competition.”

“IBM had patents on MCA system features and required MCA systemmanufacturers to pay a license fee. As a reaction to this, in late 1988 the"Gang of Nine", led by Compaq, announced a rival bus – EISA. Offeringsimilar performance benefits, it had the advantage of being able to acceptolder XT and ISA boards.”

“MCA also suffered for being a proprietary technology. Unlike theirprevious PC bus design, the AT bus, IBM did not publicly release specificationsfor MCA and actively pursued patents to block third parties from sellingunlicensed implementations of it, and the developing PC clone market did notwant to pay royalties to IBM in order to use this new technology. The PC clonemakers instead developed EISA as an extension to the existing old AT busstandard. The 16–bit AT bus was embraced and renamed as ISA to avoid IBM's"AT" trademark. With few vendors other than IBM supporting it withcomputers or cards, MCA eventually failed in the marketplace.”

“While EISA and MCA battled it out in the server arena, the desktop PClargely stayed with ISA up until the arrival of PCI, although the VESA LocalBus, an acknowledged stopgap, was briefly popular.” [R92]

NotationsUsed for a Bus

We pause here in our historical discussion of bus design tointroduce a few terms used to characterize these busses. We begin with some conventions used to drawbusses and their timing diagrams. Hereis the way that we might represent a bus with multiple types of lines.

The big “double arrow” notation indicates a bus of a numberof different signals. Some authors callthis a “fat arrow”. Lines with similarfunction are grouped together. Theircount is denoted with the “diagonal slash” notation. From top to bottom, we have
           1.        Three data lines                                  D₂,D₁, and D₀
           2.        Two address lines                              A₁and A₀
           3.        The clock signal for the bus   F.
                       Not all bussestransmit a clock signal; the system bus usually does.

Power and ground lines usually are not shown in this type ofdiagram. Note the a bus with only onetype of signal might be drawn as a thick line with the slash, as in the 3 – bitdata bus above.

Maximum Bus Length

In general, bus length varies inversely as transmissionspeed, often measured in Hz; e.g., a
1 MHz bus can make one million transfers per second and a 2 GHz bus can maketwo billion. 
Immediately we should note that the above is not exactly true of DDR (DoubleData Rate) busses which transfer at twice the bus speed; a 500 MHz DDR bustransfers 1 billion times a second.
Note that the speed in bytes per second is related to the number of bytes pertransfer. A DDR bus rated at 400 MHz andhaving 32 data lines would transfer 4 bytes 800 million times a second, for atotal of 3.20 billion bytes per second. Note that this is the peak transfer rate.

The relation of the bus speed to bus length is due to signalpropagation time. The speed of light isapproximately 30 centimeters per nanosecond. Electrical signals on a bus typically travel at
2/3 the speed of light; 20 centimeters per nanosecond or 20 meters permicrosecond.

A loose rule of thumb in sizing busses is that the signalshould be able to propagate the entire length of the bus twice during one clockperiod. Thus, a 1 MHz signal would havea one microsecond clock period, during which time the signal could propagate nomore than twenty meters. This length isa round trip on a ten meter bus; hence, the maximum length is 10 meters. Similarly, a 1 GHz signal would lead to amaximum bus length of ten centimeters. 

The rule above is only a rough estimator, and may beincorrect in some details. Since thetypical bus lengths on a modern CPU die are on the order of one centimeter orless, we have no trouble.

Bus Classifications

It should be no surprise that, depending on the featurebeing considered, there are numerous ways to characterize busses. We have already seen one classification, whatmight be called a “mixed bus” vs. a “pure bus”; i.e., does the bus carry morethan one type of signal. Most busses areof the mixed variety, carrying data, address, and control signals. The internal CPU busses on our design carryonly data because they are externally controlled by the CPU Control Unit thatsends signals directly to the bus end points.

One taxonomy of busses refers tothem as either point–to–point vs. shared. Here is a picture of that way of looking at busses.

An example of apoint–to–pointbus might be found in the chapter on computer internal memory, where wepostulated a bus between the MBR and the actual memory chip set. Most commonly, we findshared busses with a number of devices attached.

Another way of characterizing busses is by the number of“bus masters” allowed. Abus master is a device that hascircuitry to issue command signals and place addresses on the bus. This is in distinction to a “bus slave” (politically incorrectterminology) that can only transfer data in response to commands issued by abus master. In the early designs, onlythe CPU could serve as a bus master for the memory bus. More modern memory busses allow someinput/output devices (discussed later as DMA devices) to act as bus masters andtransfer data to the memory.

Bus Clocks

Another way to characterize busses is whether the bus isasynchronous or synchronous. Asynchronous bus is one that has one ormore clock signals associated with it, and transmitted on dedicated clocklines. In a synchronous bus, the signalassertions and data transfers are coordinated with the clock signal, and can besaid to occur at predictable times.

Anasynchronousbus is one without a clock signal. Thedata transfers and some control signal assertions on such a bus are controlledby other control signals. Such a busmight be used to connect an I/O unit with unpredictable timing to the CPU. The I/O unit might assert some sort ofready signal when it can undertake atransfer and adone signal when thetransfer is complete.

In order to understand these busses more fully, it wouldhelp if we moved on to a discussion of the bus timing diagrams and signallevels.

Bus Signal Levels

Many times bus operation is illustrated with a timingdiagram that shows the value of the digital signals as a function of time. Each signal has only two values,corresponding to logic 0 and to logic 1. The actual voltages used for these signals will vary depending on thetechnology used.

A bus signal isrepresented in some sort of trapezoidal form with rising edges and fallingedges, neither of which is represented as a vertical line. This convention emphasizes that the signalcannot change instantaneously, but takes some time to move between logic highand low. Here is a depiction of the busclock, represented as a trapezoidal wave.

Here is a samplediagram, showing two hypothetical discrete signals. Here the discrete signal B# goes low duringthe high phase of clock T1 and stays low. Signal A# goes low along with the second half of clock T1 and stays lowfor one half clock period.

A collection ofsignals, such as 32 address lines or 16 data lines cannot be represented withsuch a simple diagram. For each ofaddress and data, we have two important states; the signals are valid, andsignals are not valid

For example,consider the address lines on the bus. Imagine a 32–bit address. At sometime after T₁, the CPU asserts an address on the address lines. This means that each of the 32 address linesis given a value, and the address is valid until the middle of the high part ofclock pulse T2, at which the CPU ceases assertion.

Having seen these conventions, it is time to study a pair oftypical timing diagrams. We first studythe timing diagram for a synchronous bus. Here is a read timing diagram.

What we have here is a timing diagram that covers three fullclock cycles on the bus. Note thatduring the high clock phase of T₁, the address is asserted on thebus and kept there until the low clock phase of T₃. Before and after these times, the contents ofthe address bus are not specified. Notethat this diagram specifies some timing constraints. The first is T_AD, the maximumallowed delay for asserting the address after the clock pulse if the memory isto be read during the high phase of the third clock pulse.

Note that the memory chip will assert the data for one halfclock pulse, beginning in the middle of the high phase of T₃. It is during that time that the data arecopied into the MBR.

Note that the three control signals of interest ( ) are asserted low. We also have another constraint T_ML,the minimum time that the address is stable before the is asserted.

The purpose of the diagram above is to indicate what has tohappen and when it has to happen in order for a memory read to be successfulvia this synchronous bus. We have fourdiscrete signals (the clock and the three control signals) as well as twomulti–bit values (memory address and data).

For the discrete signals, we are interested in the specificvalue of each at any given time. For themulti–bit values, such as the memory address, we are only interested incharacterizing the time interval during which the values are validly assertedon the data lines.

Note that the more modern terminology for the three controlsignals that are asserted low would beMREQ#,RD#, andWAIT#. 

The timing diagram for an asynchronous bus includes someadditional information. Here the focusis on the protocol by which the two devices interact. This is also called the “handshake”. The bus master asserts MSYN# and the busslave responds with SSYN# when done.

The asynchronous bus uses similar notation for both thediscrete control signals and the
multi–bit values, such as the address and data. What is different here is the “causal arrows”, indicating that thechange in one signal is the causation of some other event. Note that the assertion ofMSYN# causes the memory chip to placedata on the bus and assertSSYN#. That assertion causesMSYN# to be dropped, data to be no longer asserted, and thenSSYN# to drop.

MultiplexedBusses

A bus may be either multiplexed or non–multiplexed. In amultiplexedbus, bus data and address share the same lines, with a control signal todistinguish the use. Anon–multiplexed bus has separate linesfor address and data. The multiplexedbus is cheaper to build in that it has fewer signal lines. A non–multiplexed bus is likely faster.

There is a variant of multiplexing, possibly called “address multiplexing” that is seen onmost modern memory busses. In thisapproach, an N–bit address is split into two (N/2)–bit addresses, one a rowaddress and one a column address. Theaddresses are sent separately over a dedicated address bus, with the controlsignals specifying which address is being sent.

Recall that most modern memory chips are designed for suchaddressing. The strategy is to specify arow, and then to send multiple column addresses for references in thatrow. Some modern chips transmit in burstmode, essentially sending an entire row automatically.

Here, for reference, is the control signal description fromthe chapter on internal memory.

Moreon Real Bus Architecture

Here we offer some information on a now–obsolete bus of somehistorical interest. For those that arenot interested in the history, we note that this presents a chance to discusssome issues related to bus design that have not yet been broached.

The bus in question is the PDP–11 Unibus™, manufactured inthe 1970’s by the Digital Equipment Corporation. We first discuss the use of groundlines. Ground lines on the bus have twopurposes
           1.        to complete the electrical circuits, and
           2.        to minimize cross–talk between the signal lines.

Cross–talk occurs when a signal onone bus line radiates to and is copied by another bus line. Placing a ground line between 2 linesminimizes this. This small bus ismodeled on the Unibus.

The variety of signals that can be placed on a bus is seenin the following table adapted from the PDP-11 Peripherals Handbook [R3]. Note that this bus operates as anasynchronous bus, which will allow slower I/O devices to use the bus.

Figure: PDP-11 UNIBUS CONTROLSIGNALS

We seeabove the expected data and address lines, though noting the small addresssize. We see most of the expectedcontrol lines (MSYN# and SSYN#). Whatabout the priority lines? These are controllines that allow an I/O device to signal the CPU that it is ready to transferdata.

The Bozseries of computer designs follows the PDP–11 model in that it has fourpriority levels for I/O devices. Whilethis strategy will be discussed more fully in a future chapter, we note herethat the bus used for the I/O devices to communicate with the CPU must have twolines for each level in order for the interrupt structure to function.

The above figure suggests that the PDP–11 can operate in oneof eight distinct priority levels, from 0 to 7. The upper four levels (4, 5, 6, and 7) are reserved for handling I/Odevices. The lower four levels (0, 1, 2,and 3) were probably never fully implemented. Normal programs run at priority 0, and the other three levels (1, 2, and3) are probably ignored. At each level,the bus provides two lines: BR (bus request) that is the interrupt line, and BG(bus grant) that signals the device to start transferring data. As indicated above, we shall say more on thisvery soon.

ModernComputer Busses

The next major step in evolution of the computer bus tookplace in 1992, with the introduction by Intel of the PCI (Peripheral ComponentInterconnect) bus. By 1995, the bus wasoperating at 66 MHz, and supporting both a 32–bit and 64–bit address space.

According to Abbott [R64], “PCI evolved, at least in part,as a response to the shortcomings of the then venerable ISA bus. … ISA began to run out of steam in 1992, whenWindows had become firmly established.” Revision 1 of the PCI standard was published in April 1993.

The PCI bus standard has evolved into the PCI Expressstandard, which we shall now discuss.

PCIExpress

PCI Express(Peripheral Component Interconnect Express) is a computer expansion cardstandard designed to replace the older PCI bus standard. The name is abbreviated as “PCIe”. This is viewed as a standard for computerexpansion cards, but really is a standard for the communication link by which acompliant device will communicate over the bus.

According toWikipedia [R93], PCIe 3.0 (August 2007) is the latest standard. While an outgrowth of the original PCI busstandard, the PCIe is not compatible with that standard at the hardwarelevel. The PCIe standard is based on anew protocol for electrical signaling.
This protocol is built on the concept of a lane, which we must define. A PCI connection can comprise from 1 to 32lanes. Here are some capacity quotesfrom Wikipedia

                                               PerLane                                 16–LaneSlot
Version 1                                250MB/s                               4 GB/s
Version 2                                500MB/s                               8 GB/s
Version 3                                1GB/s                                    16GB/s

Whatis a Lane?

Alane is pair of point–to–point serial links, in other words the lane is afull–duplex link, able to communicate in two directions simultaneously. Each of the serial links in the pair handlesone of the two directions.

By definition, aserial link transmits one bit at atime. By extension, alane may transmit two bits at any onetime, one bit in each direction. One mayview aparallel link, transmitting multiplebits in one direction at any given time, as a collection of serial links. The only difference is that a parallel linkmust provide for synchronization of the bits sent by the individual links.

DataTransmission Codes

The PCIestandard is byte oriented, in that it should be viewed logically as afull–duplex byte stream. What isactually transmitted? The association ofbits (transmitted or received) with bytes is handled at the Data Linklayer. Suppose a byte is to betransmitted serially.

The conversionfrom byte data to bit–oriented data for serial transmission is done by a shiftregister. The register takes in eightbits at a time and shifts out one bit at a time. The bits, as shifted out, are stillrepresented in standard logic levels. Theserial transmit unit takes the standard logic levels as input, and convertsthem to voltage levels appropriate for serial transmission.

ThreePossible Transmission Codes

The serialtransmit unit sends data by asserting a voltage on the serial link. The simplest method would be as follows.
           To transmit a logic 1, assert+5 volts on the transmission line.
           To transmit a logic 0, assert0 volts on the transmission line.

There are verymany problems with this protocol. It isnot used in practice for any purpose other than transmitting power. The two main difficulties are asfollows. The first problem is that oftransmitting power. If the averagevoltage (over time) asserted by a transmitter on a line is not zero, then thetransmitter is sending power to the receiver. This is not desirable. The answerto this is to develop a protocol such that the time–averaged voltage on theline is zero. Such a protocol might callfor enough changes in the voltage level to allow for data framing. Standard methods for link management use codesthat avoid these problems. Two of themore common methods used are NRZ and NRZI.

Non–Return–to–Zero coding transmits by assertingthe following voltages:
           For a logic 1, it asserts apositive voltage (3.0 – 5.0 volts) on the link.
           For a logic 0, it asserts anegative voltage (–3.0 to –5.0 volts).

Non–Return–to–Zero–Invert is amodification of NRZ, using the same
voltage levels.

TheProblem of Noise

One problem withthese serial links is that they function as antennas. They will pick up any stray electromagneticradiation if in the radio range.

In other words,the signal received at the destination might not be what was actuallytransmitted. It might be the originalsignal, corrupted by noise. The solutionto the problem of noise is based on the observation that two links placed inclose proximity will receive noise signals that are almost identical. To make use of this observation, we usedifferential transmitters[ R94]to send the signals anddifferential receivers to reconstructthe signals.

In differentialtransmission, rather than asserting a voltage on a single output line, thetransmitter asserts two voltages: +V/2 and –V/2. A +6 volt signal would be asserted as two: +3volts and –3 volts. A –8 volt signalwould be asserted as two: –4 volts and +4 volts.

Here are thestandard figures for a differential transmitter and differential receiver. The standard receiver is an analog subtractor,here giving V/2 – (–V/2) = V.

           DifferentialTransmitter                                             DifferentialReceiver

Noisein a Differential Link

We now assumethat the lines used to transmit the differential signals are physically closetogether, so that each line is subject to the same noise signal.

Here thereceived signal is the difference of the two voltages input to the differentialreceiver. The value received is ( V/2 +N(t) ) – ( –V/2 + N(t) ) = V, thedesired value.

GroundOffsets in Standard Links

All voltages aremeasured relative to a standard value, called“ground”. Here is thecomplete version of the simple circuit that we want to implement.

Basically, thereis an assumed second connection between the two devices. This second connection fixes the zero levelfor the voltage.

There is nonecessity for the two devices to have the same ground. Suppose that the ground for the receiver isoffset from the ground of the transmitter.

The signal sentout as +V(t) will be received as V(t) – V_O. Here again, the subtractor in thedifferential receiver handles this problem.

The signaloriginates as a given voltage, which can be positive, negative, or 0. The signal is transmitted as the pair (+V/2,–V/2). Due to the ground offset, thesignal is taken in as
(+V/2 – V_O, –V/2 – V_O), interpreted as (+V/2 – V_O)– (–V/2 – V_O) = +V/2 – V_O + V/2 + V_O = V.

The differentiallink will correct for both ground offset and line noise at the same time.

Note:The author of this text became interested in the PCIe bus standardafter reading product descriptions for the NVIDIA C2070 Computing Processor(www.nvidia.com). This is a very highperformance coprocessor that attaches to the host via a 16–lane PCIe bus. What is such a bus? What is a lane? Professors want to know.

Interfacesto Disk Drives

The disk driveis not a stand–alone device. In order tofunction as a part of a system, the disk must be connected to the motherboardthrough a bus. We shall discuss detailsof disk drives in the next chapter. Inthis one, we focus on two popular bus technologies used to interface a disk:ATA and SATA. Much of this material isbased on discussions in chapter 20 of the book on memory systems by BruceJacob, et al [R99].

The top–levelorganization is shown in the figure below. We are considering the type of bus used to connect the disk drive to themotherboard; more specifically, the host controller on the motherboard to thedrive controller on the disk drive. Whilethe figure suggests that the disk is part of the disk drive, this figureapplies to removable disks as well. Theimportant feature is the nature of the two controllers and the protocol forcommunication between them.

One of theprimary considerations when designing a disk interface, and the bus toimplement that interface, is the size of the drive controller that is packagedwith the disk. As Jacob [R99] put it:

“In the earlydays, before Large Scale Integration (LSI) mad adequate computational powereconomical to be put in a disk drive, the disk drives were ‘dumb’ peripheraldevices. The host system had tomicromanage every low–level action of the disk drive. … The host system had toknow the detailed physical geometry of the disk drive; e.g., number ofcylinders, number of heads, number of sectors per track, etc.”

“Two thingschanged this picture. First, with theemergence of PCs, which eventually became ubiquitous, and the low–cost diskdrives that went into them, interfaces became standardized. Second, large–scale integration technology inelectronics made it economical to put a lot of intelligence in the disk sidecontroller”

As of Summer2011, the four most popular interfaces (bus types) were the two varieties ofATA (Advanced Technology Attachment, SCSI (Small Computer Systems Interface0,and the FC (Fibre Channel). The SCSI andFC interfaces are more costly, and are commonly used on more expensivecomputers where reliability is a premium. We here discuss the two ATA busses.

The ATAinterface is now managed by Technical Committee 13 of INCITS (www.t13.org), theInternational Committee for Information Technology Standards (www.incits.org). The interface was so named because it wasdesigned to be attached to the IBM PC/AT, the “Advanced Technology” version ofthe IBM PC, introduced in 1984. To quoteJacob again:

“The first harddisk drive to be attached to a PC was Seagate’s ST506, a 5.25 inch form factor5–MB drive introduced in 1980. The driveitself had little on–board control electronics; most of the drive logic residedin the host side controller. Around thesecond half of the 1980’s, drive manufacturers started to move the controllogic from the host side and integrate it with the drive. Such drives became known as IDE (IntegratedDrive Electronics) drives.”

In recent years,the ATA standard has being explicitly referred to at the “PATA” (Parallel ATA)standard to distinguish it from the SATA (Serial ATA standard) that is nowbecoming popular. The original PATAstandard called for a 40–wire cable. Asthe bus clock rate increased, noise from crosstalk between the unshieldedcables became a nuisance. The new designincluded 40 extra wires, all ground wires to reduce the crosstalk.

As an example ofa parallel bus, we show a picture of the PDP–11 Unibus. This had 72 wires, of which 56 were devotedto signals, and 16 to grounding. Thisbus is about 1 meter in length.

Figure: TheUnibus of the PDP–11 Computer

Up to thispoint, we have discussed parallel busses. These are busses that transmit N data bits over N data lines, such asthe Unibus™ that used 16 data lines to transmit two bytes per transfer. Recently serial busses have become popular;especially the SATA (Serial Advanced Technology Attachment) busses used toconnect internally mounted disk drives to the motherboard. There are two primary motivations for thedevelopment of the SATA standard: clock skews and noise.

The problem ofclock skew is illustrated by the following pair of figures. The first figure shows a part of the timingdiagram for the intended operation of the bus. While these figures may be said to be inspired by actual timingdiagrams, they are probably not realistic.

In the above figure, the control signals MREQ# and RD# areasserted simultaneously one half clock time, after the address becomesvalid. The two are simultaneouslyasserted for two clock times, after which the data are read.

We now imagine what could go wrong when the clock time isvery close to the gate delay times found in the circuitry that generates thesecontrol signals. For example, let usassume a 1 GHz bus clock with a clock time of one nanosecond. The timing diagram above calls for the twocontrol signals, MREQ# and RD#, to be asserted 0.5 nanoseconds (500picoseconds) after the address is valid. Suppose that the circuit for each of these is skewed by 0.5 nanoseconds,with the MREQ# being early and the RD# being late.

What we have in this diagram is a mess, one that probablywill not lead to a functional read operation. Note that MREQ# and RD# are simultaneously asserted for only an instant,far too short a time to allow any operation to be started. The MREQ# being early may or may not be aproblem, but the RD# being late certainly is. A bus with these skews will not work.

As discussed above, the ribbon cable of the PATA bus has 40unshielded wires. These are susceptibleto cross talk, which limits the permissible clock rate. What happens is that crosstalk is a transientphenomenon; the bus must be slow enough to allow its effects to dissipate.

We have already seen a solution to the problem of noise whenwe considered the PCI Express bus. Thisis the solution adopted by the SATA bus. The standard SATA bus has a seven–wire cable for signals and a separatefive–wire cable for power. Theseven–wire cable for data has three wires devoted to ground (noise reduction)and four wires devoted to a serial lane, as described above for PCIExpress. As noted above in thatdiscussion, the serial lane is relatively immune to noise and crosstalk, whileallowing for very good transmission speeds.

One might note that parallel busses are inherently fasterthan serial busses. An N–bit bus willtransmit data N times faster than a 1–bit serial bus. The experience seems to be that the datatransmission rate can be so much higher on the SATA bus than on a parallel bus,that the SATA bus is, in fact, the faster of the two. Data transmission on these busses is rated inbits per second. In 2007, according toJacob [R99] “SATA controllers and disk drives with 3 Gbps are starting toappear, with 6 Gbps on SATA’s roadmap.” The encoding used is called “8b/10b”, in which an
8–bit byte is padded with two error correcting bits to be transmitted as 10bits. The two speeds above correspond to300 MB per second and 600 MB per second.