TRIPS Technical Overview
The TRIPS project has developed technology scalable processor andmemory system technologies for nanoscale microprocessor chips. Thesetechnologies are intended to mitigate increasing on-chip communicationlatency, to provide power efficiency and reduce design complexity forhigh-performance systems, and to provide programmers with familiarinstruction execution models.
Key Technologies and Innovations
- Explicit Data Graph Execution (EDGE) instruction set architecture
- Scalable and distributed processor core composed of replicated heterogeneous tiles
- Non-uniform cache architecture and implementation
- On-chip networks for operands and data traffic
- Configurable on-chip memory system with capability to shiftstorage between cache
and physical memory - Composable processors constructed by aggregating homogeneous processor tiles
- Compiler algorithms and an implementation that create atomicallyexecutable blocks
of code - Spatial instruction scheduling algorithms and implementation
TRIPS Hardware and Software
To enable scalable and distributed processor cores, the TRIPS teamdeveloped Explicit Data Graph Execution (EDGE) architectures and hasimplemented the architecture in a custom ASIC TRIPS prototype chip.Unlike traditional processor architectures that operate at thegranularity of a single instruction, EDGE ISAs support large graphs ofcomputation mapped to a flexible hardware substrate, with instructionsin each graph communicating directly with other instructions, ratherthan going through a shared register file. This capability not onlyreduces design complexity, but amortizes and execution overheads overa large graph of instructions.
The TRIPS microarchitecture is fundamentally distributed and composedof tiles communicating via control and operand networks. Theimplementation includes protocols that enable the disparate tiles toact cohesively as a single high-performance processor. The TRIPS teamhas also developed a scalable on-chip memory system which is composedof multiple memory banks connected via a high-bandwidth on-chipnetwork. The memory banks can be configured to operate as anon-uniform cache (NUCA), a novel scalable on-chip memory systemdeveloped by the TRIPS team.
The TRIPS processor executes code generated by a custom compiler fromsequential C or Fortran programs. The compiler includes algorithmsdesigned to create large blocks that can execute atomically, accordingto the EDGE specifications. In addition, the compiler includes aspatial instruction scheduler which places instructions to be executedon the distributed execution substrate such that communication latencyand contention among the tiles are minimized.
Prototype
In 2003, the TRIPS team began the implementation of a prototype systemincluding a custom ASIC, custom system boards, and custom softwaretools. First silicon was delivered on September 27, 2006. Each TRIPSchip contains two scalable processor cores, each of which can executeup to 16 instructions per cycle. The prototype system can be scaledup to 32 processor chips for a peak performance approaching 500gigaflops. The team will use the prototype to demonstrate theend-to-end application capabilities of EDGE hardware and software, toidentify performance bottlenecks in the architecture, and to continueto develop and refine algorithms in the compiler.
Targetted Applications
TRIPS is designed to be a general purpose architecture that performswell across a wide range of applications. The current applicationsuite includes desktop/workstation applications (SPEC), embeddedapplications (EEMBC), and signal processing applications. The TRIPSteam is currently tuning compiler algorithms and adding moreapplications to the test suite.
TRIPS Team
The TRIPS processor has been in development for three years, and iscurrently funded by the Defense Advanced Research Projects Agency's(DARPA). Polymorphous Computing Architectures program. The TRIPS teamconsists of 30 faculty members, research scientists, graduatestudents, undergraduates, and post docs, and is led byProfessorsDoug Burger andStephen W. Keckler. The TRIPS compiler effort is led by ProfessorKathryn McKinley.
The University of Texas at Austin, Department of Computer Sciences
Taylor Hall 2.124, Austin, TX 78712-1188, 512.471.7316, fax 471.8885