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A C-Program that simulates Virtual Memory Management based on a text file input of logical addresses which represents sequential instructions with address range 0 thru 2¹⁶ - 1. See theProject Report for more details regarding usage.

This project is the design and implementation of a standalone virtual memory manager, where there is a software-managed TLB. The program is responsible to (1) load afile containing a list of logical addresses, (2) translate logical addresses into physical addresses for a virtual address space of size 2¹⁶ = 65,536 bytes, and (3) output the value of the byte stored at the translated physical address.

The program reads a file containing a list of 32-bit integer numbers, which represent 32-bit logical addresses. It should be noted that the program only deals with 16-bit addresses. Thus, this simulation implements masking for the rightmost 16 bits of each logical address loaded from the file.

The page table size is 2⁸ bytes; the TLB contains 16 entries. The page size is 2^8^ bytes, which is the same as the frame size. There are a total of 256 frames in the physical memory, meaning that the total physical memory capability is 65,536 bytes (i.e., 256 frames * 256 bytes/frame). The system parameters of the simulated virtual memory is summarized below.

• Page table size:2⁸
• Number of TLB entries:16
• Page size:2⁸ bytes
• Frame size:2⁸ bytes
• Number of frames:256
• Physical memory size:65,536 bytes

This virtual memory system implements demand paging. The backing store is simulated by a file called “BACKING_STORE.bin”. BACKING_STORE is a binary file of 65,536 bytes. When a page fault occurs, the virtual memory system will perform the following four steps:

• Step 1: read a 256-byte page from the file BACKING_STORE and
• Step 2: store the loaded page frame in the physical memory.
• Step 3: Update the page table
• Step 4: Update the TLB

For example, if a logical address with page number 15 triggers a page fault, your virtual memory system will read in page 15 from the file BACKING_STORE. Then, the loaded page frame is placed in the physical memory. After the page frame is fetched from the disk, the page table and the TLB will be updated accordingly. Subsequent access of page 15 will be referenced by accessing either the TLB or the page table.

• Compiled and tested using clang compiler:$ clang -o vm_sim vm_sim.c vmtypes.c
• ALSO Compiled and tested using gcc:$ gcc -o vm_sim vm_sim.c vmtypes.c
• Created Makefile with gcc as Constant
• SIMPLY download this project and executemake in command line
• Execute program with$ ./vm_sim InputFile.txt or use an appropriate[input].txt file

• For how to create smart arrays
• Dynamic Allocation of 2D Array in struct
• For creating physical memory struct
• More dynamic allocation
• Double Pointer Return Type
• How to Perform Bit Masking
• Proper malloc() error output and exiting
• How to use fgets() function
• How to measure clock time
• NOTE: Other sources were also used to gain understanding of Virtual Memory Management concepts

Welcome to Don's VM Simulator Version 1.0Number of logical pages: 256Page size: 256 bytesPage Table Size: 256TLB Size: 16 entriesNumber of Physical Frames: 256Physical Memory Size: 65536 bytesDisplay All Physical Addresses? [y/n]: nChoose TLB Replacement Strategy [1: FIFO, 2: LRU]: 1

If FIFO is selected, program displays to console:

Results Using FIFO Algorithm: Number of translated addresses = 1000Page Faults = 244Page Fault Rate = 24.400 %TLB Hits = 51TLB Hit Rate = 5.100 %Average time spent retrieving data from backing store: 5.537 millisec

If LRU is selected, program displays to console:

Welcome to Don's VM Simulator Version 1.0Number of logical pages: 256Page size: 256 bytesPage Table Size: 256TLB Size: 16 entriesNumber of Physical Frames: 256Physical Memory Size: 65536 bytesDisplay All Physical Addresses? [y/n]: nChoose TLB Replacement Strategy [1: FIFO, 2: LRU]: 2-----------------------------------------------------------------------------------Results Using LRU Algorithm: Number of translated addresses = 1000Page Faults = 244Page Fault Rate = 24.400 %TLB Hits = 56TLB Hit Rate = 5.600 %Average time spent retrieving data from backing store: 4.598 millisec-----------------------------------------------------------------------------------

If user chooses to display physical addresses, a similar output will immediately precede the results:

-----------------------------------------------------------------------------------Virtual address: 16916Physical address: 20Value: 0Virtual address: 62493Physical address: 285Value: 0Virtual address: 30198Physical address: 758Value: 29Virtual address: 53683Physical address: 947Value: 108Virtual address: 40185Physical address: 1273Value: 0Virtual address: 28781Physical address: 1389Value: 0Virtual address: 24462Physical address: 1678Value: 23Virtual address: 48399Physical address: 1807Value: 67Virtual address: 64815Physical address: 2095Value: 75Virtual address: 18295Physical address: 2423Value: -35Virtual address: 12218Physical address: 2746Value: 11Virtual address: 22760Physical address: 3048Value: 0Virtual address: 57982Physical address: 3198Value: 56Virtual address: 27966Physical address: 3390Value: 27...-----------------------------------------------------------------------------------