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xilinx-vitis

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triSYCL /sycl

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM

llvm clang xilinx-fpga sycl cpp20 accelerators xilinx-vitis trisycl oneapi-dpc sycl-compilation dpc-toolchain

UpdatedNov 4, 2024
C++

TurakhiaLab /DP-HLS

HLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA

bioinformatics fpga hls dynamic-programming hardware-acceleration fpga-accelerator high-level-synthesis xilinx-vitis

UpdatedJun 20, 2025
C++

nodamushi /vivado_cmake_module

CMake for Xilinx Vivado/Vitis

cmake xilinx-vivado xilinx-hls xilinx-vitis

UpdatedJun 13, 2023
CMake

aryan-programmer /axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls axi-memory-mapped

UpdatedNov 21, 2023
TeX

FrankKesel /xilinx_tools

Xilinx Tools Tutorials

fpga vhdl xilinx xilinx-fpga xilinx-vivado high-level-synthesis vitis xilinx-vitis vitis-hls

UpdatedSep 23, 2025
Jupyter Notebook

aryan-programmer /axi_stream_array_sum_microblaze

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado microblaze axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls

UpdatedDec 3, 2023
C

ArioKian /Xilinx-Zynq7000-ZynqUltraScalePlus-PS-SdCard-Drivers

Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.

zynq xilinx xilinx-fpga zynq-7010 xilinx-vivado zynq-7000 xilinx-sdk xilinx-zynq zynq-example-project zynq-7020 xilinx-vitis zynq-ultrascale

UpdatedMar 6, 2024
C

justin-marian /cla-16bits-adder

Carry-Lookahead 16-bits Adder (CLA16) computes sums by rapidly determining carry bits through parallel processing.

cpp 16bits 4bits carry-look-ahead-adder xilinx-vitis

UpdatedMar 14, 2024
C++

efetunca /Zynq-7000-TFTP-Server

A TFTP server running on Zynq-7000

zynq xilinx tftp tftp-server zynq-7000 xilinx-sdk xilinx-zynq vitis xilinx-vitis

UpdatedMay 15, 2024
C

harshonyou /TSP-on-FPGA

FPGA-based hardware-accelerated, parallelized, and highly optimized solution for solving the Travelling Salesperson Problem (TSP) using Xilinx Zynq-7000 on a Digilent Zybo Z7-10 board, featuring FreeRTOS for real-time task management.

fpga udp freertos tsp-problem xilinx-vivado zynq-7000 xilinx-hls xilinx-vitis

UpdatedAug 15, 2024
C

dennisleexyz /vitis-2019.2

(Arch Linux package) Xilinx FPGA/CPLD design suite downgraded to version 2019.2

fpga aur archlinux arch arch-linux xilinx vivado aur-packages xilinx-fpga xilinx-vivado fpga-programming vitis vivado-installer xilinx-vitis vivado-vitis

UpdatedDec 25, 2023
Shell

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