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#

xilinx-fpga

Here are 226 public repositories matching this topic...

openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

  • UpdatedNov 6, 2025
  • C
prjxray

Documenting the Xilinx 7-series bit-stream format.

  • UpdatedJun 5, 2025
  • Python
f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

  • UpdatedNov 5, 2025
  • Jupyter Notebook

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

  • UpdatedJun 24, 2021
  • Verilog
blaze

blaze is a Rust library for ZK acceleration on Xilinx FPGAs.

  • UpdatedOct 22, 2024
  • Rust

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM

  • UpdatedNov 4, 2024
  • C++

Xilinx Virtual Cable Server for Raspberry Pi

  • UpdatedMar 14, 2022
  • C

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

  • UpdatedJun 6, 2020
  • C++
yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

  • UpdatedMay 14, 2024
  • Verilog

Minimal DVI / HDMI Framebuffer

  • UpdatedAug 9, 2020
  • Verilog

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

  • UpdatedFeb 9, 2022
  • SystemVerilog
prjxray-db

Project X-Ray Database: XC7 Series

  • UpdatedDec 14, 2021
  • Shell

💰 A simplified version of an FPGA bitcoin miner 💰

  • UpdatedJul 9, 2019
  • VHDL

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

  • UpdatedAug 12, 2017
  • Verilog

Re-coded Xilinx primitives for Verilator use

  • UpdatedJun 24, 2025
  • Verilog

building blocks for accelerating ZK proofs over binary fields

  • UpdatedJun 19, 2025
  • Verilog

Open-source CSI-2 receiver for Xilinx UltraScale parts

  • UpdatedJul 10, 2019
  • Verilog

中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session

  • UpdatedJun 24, 2017
  • Verilog

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.

  • UpdatedJan 23, 2024
  • Scala

Design and Implementation of a Simple-As-Possible 1 (SAP-1) Computer using an FPGA and VHDL.

  • UpdatedFeb 15, 2023
  • VHDL

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