Simple VHDL examples using ghdl as compiler and wave generating

• UpdatedJun 21, 2022
• VHDL

all projects of vhdl course of university

• UpdatedSep 19, 2021
• VHDL

Forked from ZIKOAR's 32-bit-processor-with-vhdl repository.

• UpdatedFeb 27, 2025
• VHDL

A simple VHDL testbench generator

• UpdatedMay 28, 2021
• VHDL

A resource-friendly VHDL model for large memory simulations

• UpdatedSep 26, 2021
• VHDL

A simple VHDL test bench generator (for combinational logic) written in Python

• UpdatedMay 13, 2020
• Python

Reusable HDL modules, packages, and testbench utilities for FPGA and ASIC development, supporting both VHDL and Verilog.

• UpdatedSep 25, 2025
• VHDL

App that Generate VHDL Code and Testbench template file

• UpdatedJan 17, 2025
• HTML

A simple python script to generate a VHDL testbench template given an entity-architecture declaration passed as argument(s) as a file(s)

• UpdatedJan 2, 2025
• Python

GHDL Compiler Definition for CMake

• UpdatedNov 28, 2021
• CMake

This repository contains the source codes for design of circuits written in VHDL using Xilinx (14.7), which were practiced as a part of my CA lab during my BTech 4th semester.

• UpdatedMay 30, 2024
• VHDL

A 32-bit VHDL processor with 26 instructions, including jumps, branches, and function calls. Implementing an FSM for execution control and testing using Quartus and ModelSim.

• UpdatedFeb 25, 2025
• VHDL

A VHDL code base that contains Utility Packages for both HDL and Testbenches

• UpdatedAug 19, 2025
• VHDL

• UpdatedOct 22, 2022
• VHDL

• UpdatedMar 9, 2022
• VHDL

VHDL Logic Gates with Testbench – single-level project for simulation & learning

• UpdatedNov 9, 2025
• VHDL

An implementation of MIPS microprocessor (Single-Cycle) in VHDL with a testbench avaliable.

• UpdatedOct 10, 2024
• VHDL

Final Project - Reti Logiche. Politecnico di Milano, A.A. 2019-2020

• UpdatedDec 22, 2020
• VHDL

implementation of 4-bit BCD up/down counter. The counter work as follows: ● If input X = 0, the counter counts up. Otherwise, it counts down. ● If counting up, the counter’s value should be: 0000, 0001, 0010... ● If counting down: 0010, 0001, 0000...

• UpdatedOct 7, 2022
• VHDL

CPRE488 MP1 - VHDL AXI4-Lite IP for 6-ch PPM capture & generation on ZedBoard, plus a C app for relay/debug, record/play, and filter modes; Vivado/Vitis + Nix dev env.

• UpdatedMar 21, 2025
• HTML