Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…

• UpdatedNov 13, 2024
• Verilog

Image Processing Toolbox in Verilog using Basys3 FPGA

• UpdatedSep 19, 2023
• VHDL

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

• UpdatedJul 17, 2022
• Verilog

5-stage pipelined 32-bit MIPS microprocessor in Verilog

• UpdatedApr 3, 2020
• Verilog

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…

• UpdatedJan 29, 2024
• Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

• UpdatedJul 31, 2022
• Verilog

DDR2 memory controller written in Verilog

• UpdatedFeb 28, 2012
• Verilog

Implementing Different Adder Structures in Verilog

• UpdatedSep 3, 2019
• Verilog

NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）

• UpdatedMar 19, 2024
• VHDL

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

• UpdatedOct 7, 2022
• Verilog

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

• UpdatedNov 25, 2020
• Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

• UpdatedNov 30, 2022
• Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

• UpdatedJul 18, 2020
• JavaScript

Solution to COA LAB Assgn, IIT Kharagpur

• UpdatedJan 10, 2019
• Verilog

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

• UpdatedMay 10, 2019
• Verilog

Single Cycle RISC MIPS Processor

• UpdatedSep 17, 2021
• Verilog

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

• UpdatedSep 30, 2023

miniSpartan6+ (Spartan6) FPGA based MP3 Player

• UpdatedSep 2, 2019
• Verilog

An 8 input interrupt controller written in Verilog.

• UpdatedMar 22, 2012
• Verilog

Hardware Viterbi Decoder in verilog

• UpdatedMay 28, 2019
• Verilog