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systemverilog

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verible

chipsalliance /verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

productivity parser formatter analysis style-linter linter language-server-protocol syntax-tree lexer yacc systemverilog hacktoberfest lsp-server systemverilog-parser systemverilog-developer sv-lrm verible

UpdatedAug 29, 2025
C++

clash-lang /clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

UpdatedNov 6, 2025
Haskell

pulp-platform /axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

UpdatedOct 27, 2025
SystemVerilog

hdl-util /hdmi

Send video/audio over HDMI on an FPGA

audio video fpga intel xilinx vivado altera hdmi systemverilog dvi quartus hdlmake

UpdatedFeb 3, 2024
SystemVerilog

splinedrive /kianRiscV

RISC-V XV6/Linux SoC, marchID: 0x2b

linux asic cpu fpga x11 riscv verilog xv6 systemverilog mmu soc bare-metal rv32ima chipdesign tinytapeout sv32

UpdatedNov 3, 2025
Verilog

MikePopoloski /slang

SystemVerilog compiler and language services

parse compiler slang verilog language-service systemverilog

UpdatedNov 6, 2025
C++

veryl

veryl-lang /veryl

Veryl: A Modern Hardware Description Language

rust rtl verilog systemverilog hdl

UpdatedNov 6, 2025
Rust

WangXuan95 /FPGA-FOC

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

fpga motor verilog systemverilog field-oriented-control bldc pmsm foc svpwm

UpdatedSep 15, 2023
Verilog

olofk /edalize

An abstraction library for interfacing EDA tools

fpga simulation vhdl eda verilog xilinx synthesis vivado altera systemverilog icestorm lattice icarus-verilog modelsim ghdl yosys verilator riviera-pro fossi spyglass

UpdatedOct 31, 2025
Python

zachjs /sv2v

SystemVerilog to Verilog conversion

conversion verilog systemverilog yosys

UpdatedNov 2, 2025
Haskell

TerosTechnology /vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

fpga vhdl verilog systemverilog

UpdatedSep 22, 2025
VHDL

openhwgroup /core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

verification systemverilog uvm risc-v

UpdatedOct 16, 2025
Assembly

trivialmips /nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

cpu fpga mips xilinx fpga-soc-linux systemverilog fpga-soc

UpdatedJul 7, 2020
SystemVerilog

dalance /svls

SystemVerilog language server

rust language-server verilog systemverilog

UpdatedNov 4, 2025
Rust

dalance /sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017

rust parser verilog systemverilog rust-crate

UpdatedNov 4, 2025
Rust

pymtl /pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

python rtl verilog systemverilog hdl open-source-hardware pymtl hardware-generation open-source-eda multi-level-modeling cycle-level-modeling

UpdatedAug 24, 2025
Python

rggen /rggen

Code generation tool for control and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents

UpdatedSep 13, 2025
Ruby

taichi-ishitani /tvip-axi

AMBA AXI VIP

vip systemverilog uvm axi amba axi4 amba-axi

UpdatedJun 28, 2024
SystemVerilog

chipsalliance /Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi antlr4-grammar parser-ast vpi-api vpi-standard

UpdatedSep 6, 2025
C++

WangXuan95 /USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

cpu fpga riscv rtl verilog systemverilog soc risc-v rv32i softcore

UpdatedSep 14, 2023
SystemVerilog

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