synopsys-dc
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EE577b-Course-Project
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May 6, 2020 - Verilog
learn the combinational and sequential logic circuit.
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Mar 14, 2025 - SystemVerilog
Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
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Jun 9, 2021 - Verilog
Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo
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Jul 31, 2024 - Verilog
RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.
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Dec 11, 2020 - Verilog
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Apr 3, 2020 - Verilog
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
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May 12, 2024 - SystemVerilog
My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools
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Apr 25, 2024 - Verilog
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