Movatterモバイル変換


[0]ホーム

URL:


Skip to content

Navigation Menu

Search code, repositories, users, issues, pull requests...

Provide feedback

We read every piece of feedback, and take your input very seriously.

Saved searches

Use saved searches to filter your results more quickly

Sign up
#

synopsys-dc

Here are 8 public repositories matching this topic...

Language:All
Filter by language

learn the combinational and sequential logic circuit.

  • UpdatedMar 14, 2025
  • SystemVerilog

Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

  • UpdatedJun 9, 2021
  • Verilog

Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo

  • UpdatedJul 31, 2024
  • Verilog

RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.

  • UpdatedDec 11, 2020
  • Verilog

This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).

  • UpdatedMay 12, 2024
  • SystemVerilog

My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools

  • UpdatedApr 25, 2024
  • Verilog

Improve this page

Add a description, image, and links to thesynopsys-dc topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with thesynopsys-dc topic, visit your repo's landing page and select "manage topics."

Learn more


[8]ページ先頭

©2009-2025 Movatter.jp