superscalar-cpu
Here are 9 public repositories matching this topic...
HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.
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Mar 8, 2024 - C++
Implementation of advanced branch predictors, including Perceptron and Combinational Two-Level Adaptive Predictors, within the SimpleScalar simulator. Showcases enhancements in prediction accuracy and dynamic branch prediction techniques. This is a project for PSU ECE 587: Advanced Computer Architecture
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Mar 24, 2024 - C
Implementation of a Superscalar CPU with Dynamic Scheduling which support RISC-V standard ISA with standard 'M' Extention
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Oct 20, 2021
Instructions Per Count (IPC) Study on 9-Stage Supescalar Pipeline with Out-of-Order Execution
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Mar 23, 2023 - C++
ECE552: Computer Architecture — Fall 2020.
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Dec 28, 2021 - C
Course Project - Advanced Computer Architecture - Autumn Semester 2022 - Indian Institute of Technology Bombay
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Dec 13, 2022 - VHDL
An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.
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Oct 7, 2024 - SystemVerilog
A simple cpu simulator and an analyisis of its performance.
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Oct 4, 2023 - Python
Simulator of pipelined, superscalar processor core based on RISC-V ISA
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Jan 28, 2025 - C#
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