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pipelining

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folbricht /routedns

DNS stub resolver, proxy and router with support for DoT, DoH, DoQ, and DTLS

go dns golang dot dns-server pipelining dns-client dns-over-https doh dns-over-tls dns-privacy dns-over-quic doq dns-over-dtls

UpdatedOct 20, 2025
Go

cross-platform /dspatch

The Refreshingly Simple Cross-Platform C++ Dataflow / Patching / Pipelining / Graph Processing / Stream Processing / Reactive Programming Framework

cross-platform cpp data-driven pipelines data-flow reactive-programming stream-processing header-only graph-processing dataflow fbp flow-based-programming dataflow-programming pipelining patching

UpdatedOct 7, 2025
C++

tugrul512bit /Cekirdekler

Multi-device OpenCL kernel load balancer and pipeliner API for C#. Uses shared-distributed memory model to keep GPUs updated fast while using same kernel on all devices(for simplicity).

gpu dynamic opencl zero-copy pool load-balancer parallelism gpgpu gpu-acceleration opencl-kernels gpu-computing pipelining batch-processing multi-device multi multi-gpu iterative

UpdatedJul 7, 2022
C#

cross-platform /dspatcher

Cross-Platform Graphical Tool for DSPatch

cross-platform cpp data-driven pipelines data-flow reactive-programming stream-processing graph-processing dataflow fbp flow-based-programming dataflow-programming pipelining patching

UpdatedOct 27, 2025
C++

ArtemGr /pg_async.rs

Asynchronous, HA (master-master) PostgreSQL driver on top of libpq.

database asynchronous driver postgresql high-availability libpq futures pipelining

UpdatedDec 19, 2024
Rust

amoudgl /iir-bandstop-filter

Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic

embedded fpga signal-processing filter verilog iir pipelining

UpdatedMay 6, 2017
Verilog

princeofpython /Computer-Architecture

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

cpu processor verilog pipelining alu risc-v riscv32

UpdatedMay 1, 2021
Verilog

Effect-Deprecated /query

Efficiently pipeline, batch, and cache requests to any data source

caching query functional batching pipelining

UpdatedApr 11, 2023
TypeScript

cross-platform /dspatchables

DSPatch Component Repository

cross-platform cpp data-driven pipelines data-flow reactive-programming stream-processing graph-processing dataflow fbp flow-based-programming dataflow-programming pipelining patching

UpdatedOct 27, 2025
C++

nive927 /Flight_Delay_Prediction

A two-stage predictive machine learning engine that forecasts the on-time performance of flights for 15 different airports in the USA based on data collected in 2016 and 2017.

machine-learning data-visualization feature-selection performance-metrics feature-extraction forecasts pipelining flights airports data-cleaning smote correlation-coefficient pre-processing auc-roc-curve imbalanced-classes two-stage feature-ranking flight-delay-prediction smote-oversampler random-under-sampling

UpdatedJan 10, 2024
Jupyter Notebook

fluidml /fluidml

FluidML is a lightweight framework for developing machine learning pipelines.

python data-science machine-learning deep-learning optimization parallel model-selection pipelining

UpdatedOct 20, 2023
Python

djanderson /riscv-5stage-simulator

A 5-stage pipelining RISC-V 32I simulator written in Rust.

rust simulator isa pipelining risc-v

UpdatedApr 21, 2021
Rust

yonseicasl /Kite

Kite: Architecture Simulator for RISC-V Instruction Set

education simulator pipeline memory model cache assembly architecture pipelining computer-architecture instruction-set-architecture risc-v microarchitecture instruction-set branch-prediction five-stage instruction-dependency

UpdatedJan 2, 2025
C++

stevana /pipelined-state-machines

An experiment in declaratively programming parallel pipelines of state machines.

pipelining state-machines disruptor

UpdatedMar 20, 2023
Haskell

qossayrida /PipelineProcessorDesign

Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.

verilog pipelining computer-architecture risc processor-design

UpdatedJul 15, 2024
Verilog

SIMDE-ULL /SIMDE

Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals

simulator educational learning-by-doing pipelining computer-architecture risc out-of-order superscalar learning-resources instruction-level-parallelism computer-architecture-and-organization

UpdatedNov 5, 2025
TypeScript

pouriya /pipeline

Have pipeline in Erlang

erlang pipeline metaprogramming pipelining erlang-developement pipeline-processor erlang-otp erlang-library

UpdatedJun 10, 2018
Erlang

fomightez /mini-pipelines

collection of scripts that chain together other scripts by preparing and processing/transforming data.

python shell bash pipelines bioinformatics-pipeline pipelining workflows workflow-automation

UpdatedJun 10, 2024
Python

GoLangsam /pipe

A pipers bag - generic functions to gain concurrency - batteries included :-)

go golang pipeline pipelines-as-code pipe parallel-computing channels parallelism concurency concurrent-processes concurrent-programming golang-library pipes pipelining chan concurrency-library parallel-processing golang-examples concurrency-management concurrency-patterns

UpdatedApr 18, 2020
Go

hslam /rpc

Package rpc implements a remote procedure call over TCP, UNIX, HTTP and WS. Up to 4x faster than net/rpc.

go tls fast golang code watch ping rpc batching transport server-push kqueue epoll pipelining multiplexing pb netpoll

UpdatedMay 17, 2023
Go

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