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nexys4ddr

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shinde-shantanu /FPGA_TDC

Time to Digital Converter on an FPGA

fpga verilog xilinx-vivado nexys4ddr

UpdatedOct 8, 2020
VHDL

santifs /ultrasonic-sensor

Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.

vhdl ultrasonic-sensor xilinx-fpga 7segment vhdl-modules vhdl-code nexys4ddr parking-sensor fpga-programming

UpdatedDec 5, 2019
VHDL

zhongyuchen /mips-32bit

Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board

fpga mips verilog vivado nexys4ddr

UpdatedSep 15, 2022
Verilog

g0kul /Game-of-Balance-on-Nexys4DDR

Game of Balance is an accelerometer based maze navigation game, with added features of score and life, that is built on Nexys 4 DDR development board.

c fpga verilog microblaze nexys4ddr game-of-balance softprocessor

UpdatedJan 27, 2018
VHDL

yidiwang21 /Nexys-4-Projects

Mini projects based on Xilinx Nexys 4 DDR

fpga verilog nexys4ddr

UpdatedOct 14, 2017
VHDL

7enTropy7 /Artix_7

My experiments with Nexys4 DDR Artix-7 FPGA Board

verilog nexys4ddr verilog-project fpga-programming artix-7

UpdatedOct 1, 2020
Verilog

luminoso /cr-countones

Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs

fpga finite-state-machine xilinx vivado xilinx-fpga xilinx-vivado nexys4ddr

UpdatedAug 30, 2017
VHDL

nickschiffer /parallel_unsigned_integer_multiplier

Xilinx Vivado Project

fpga verilog vivado nexys4ddr

UpdatedMar 20, 2018
Verilog

edw4rdyao /sdcard_digital_recognition

FPGA based SD card reads and displays pictures and performs digital recognition experiments.

fpga verilog sdcard digital-recognition nexys4ddr

UpdatedSep 27, 2021
Verilog

Louis-GUENEGO /NEXYS4ddr_microphone

An audio project with the NEXYS 4 ddr

audio vhdl microphone enseirb-matmeca oversampling pdm reverberation undersampling nexys4ddr automatic-volume

UpdatedApr 17, 2022
VHDL

SnrNotHere16 /FPGADivisionFloatingPoint

A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)

c sdk fpga zynq verilog xilinx floating-point hdl division xilinx-vivado microblaze zynq-7000 nexys4ddr floating-ip artix-7 floating-point-conversion

UpdatedApr 5, 2022
VHDL

nickschiffer /fsm_calculator

A finite state machine controlled calculator written using Verilog in Xilinx Vivado targeting the Nexys 4 DDR FPGA Board

fsm fpga verilog xilinx-vivado nexys4ddr

UpdatedDec 9, 2018
Verilog

SnrNotHere16 /Asynchronous-FIFO

An FPGA implementation of Cummings' Asynchronous FIFO

fpga rtl verilog xilinx synthesis systemverilog fifo uvm xilinx-fpga xilinx-vivado digilent hardware-description-language nexys4ddr universal-verification-methodology fpga-programming digilent-nexys-4-board synthesizable asynchronous-fifo uvm-verification register-transistor-level

UpdatedApr 14, 2022
SystemVerilog

shreegw /FPGA-Thermostat-Controller

A Thermostat controller designed using the temperature sensor on the Nexys-4 module

temperature-sensor i2c-sensors nexys4ddr verilog-project

UpdatedAug 22, 2025
Verilog

sromerop /ArtificialNeuron

It is my Final Degree Project of Grado de Tecnologías y Servicios de Telecomunicación in Universidad Politécnica de Madrid

fpga vhdl neural-networks artificial-neural-networks low-latency perceptron upm vhdl-code nexys4ddr artificial-neuron

UpdatedJan 24, 2019
VHDL

brown9804 /NexysDDR4-RISC-V_picorv32

Using VIVADO, Nexys DDR 4 board with RISC-V PicoRV32 CPU

vivado risc-v picorv32 nexys4ddr

UpdatedJul 11, 2025
Verilog

PongGameVerilog

jideoyelayo1 /PongGameVerilog

A Pong Game made in Verilog

fpga vivado pingpong nexys4ddr

UpdatedMay 16, 2023
SystemVerilog

shinesunnysom /Biofeedback-Game-System

CECS 490A/490B Course; Senior Project Design

verilog xilinx xilinx-fpga nexys4ddr

UpdatedJul 14, 2021
Verilog

santifs /simon-game-vhdl

VHDL game that displays incremental random sequences on an LED Matrix by creating a finite state machine and implementing RAM and ROM models.

vhdl simon-game finite-state-machine xilinx led-matrix-displays vhdl-modules vhdl-code nexys4ddr fpga-programming

UpdatedFeb 23, 2021
VHDL

iBug /Nexys4-DDR-stopwatch

A stopwatch on Digilent Nexys4 DDR written in Verilog

fpga verilog vivado nexys4ddr

UpdatedNov 28, 2018
VHDL

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