mips-processor

Some of my assembly code (examples, iterative and recursive algorithms) from Computer's Architecture course in Sapienza University, CS Bachelor's Degree 💾

cpu algorithms storage mips processor assembly asm assembler parallelism mips-assembly assembly-language assembly-language-programming mips-architecture mips-processor assembly-x86 assemblyscript recursive-algorithms asm-mars computer-hardware

UpdatedNov 10, 2024
Assembly

prantoamt /16bit_processor_design

Star12

processor-architecture cpu mips simulation processor cse mips-assembly hardware-designs computer-architecture mips-assembler logisim mips-language mips-architecture mips-processor mips-simulator computer-design-and-implementation cse332

UpdatedDec 30, 2018

jasonlovescoding /MIPS32CPU-5stage-pipelined

Star9

A 5-stage pipelined mips32 processor

verilog course-project mips-processor buaa

UpdatedMay 9, 2017
Verilog

JosiahMendes /MIPS32-T501

Star8

A low power, high performance 32-bit, 5-cycle MIPS core that implements a subset of instructions.

verilog systemverilog mips-assembler mips-processor mips32

UpdatedJun 21, 2021
Verilog

hakula139 /MIPS-CPU

Star8

A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog

pipeline cache systemverilog mips-processor branch-prediction

UpdatedDec 26, 2020
SystemVerilog

yasnakateb /MIPSProcessor

Star7

🔮 A 32-bit MIPS Processor Implementation in Verilog HDL

cpu xilinx mips-processor multicycle

UpdatedMay 18, 2022
Verilog

holden-davis-uca /MARS-UCA

Star7

Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.

java mips mips-assembly mips-assembler mips32cpu mips-language mips-architecture mips-processor mips32 mips-instructions mips-simulator

UpdatedFeb 10, 2023
HTML

yasnakateb /PipelinedMIPS

Star6

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

cpu pipeline mips verilog icarus-verilog verilog-hdl iverilog mips-processor mips-pipeline

UpdatedAug 30, 2020
Verilog

alabarjasteh /fum-mips

Star6

MIPS simulator written in Go

cpu mips concurrent-programming isa computer-architecture mips-processor mips-simulator

UpdatedAug 10, 2021
Go

SentinelSw /MipsStaticStackAnalyzer

Star6

An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler

statistics stack static-code-analysis mips static-analysis stackoverflow static analyzer mips-assembly stack-overflow static-analyzer microchip mips32cpu mips-architecture xc32 mips-processor mips32 mips-instructions microchip-pic microchippic32

UpdatedMar 30, 2022
C

Gripnook /mips-pipelined-processor

Star5

A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.

caching forwarding pipelining mips-processor branch-prediction

UpdatedApr 20, 2017
VHDL

mongrelgem /cMIPS

Star5

A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.

processor hardware-designs verilog-hdl mips-architecture mips-processor vhdl-code

UpdatedSep 3, 2019
Verilog

akankshac-073 /MIPS-5-stage-pipelined-control-and-datapath

Star5

Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding cont…

verilog computer-architecture mips-architecture mips-processor mips32 pipelined-processors mips-pipline-processor-verilog