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jesd204b
Here are 9 public repositories matching this topic...
HDL libraries and projects
- Updated
Mar 18, 2025 - Verilog
ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
ddrdspvhdlxilinxadcddcalteraddsdigital-signal-processingfirjesd204banalog-signalsserial-interfacecicdacadc-configuratorserdes-mode
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Aug 29, 2018 - VHDL
Python interface and configurator for the ADI JESD204 Interface Framework
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Feb 28, 2025 - Python
JESD204B ADC and DAC SYZYGY Pod.
- Updated
May 21, 2022
HDL libraries and projects
- Updated
Oct 6, 2022 - Verilog
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