Kactus2 is a graphical EDA tool based on the IP-XACT standard.

• UpdatedMar 13, 2025
• C++

Python-based IP-XACT parser

• UpdatedJun 13, 2024
• Python

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

• UpdatedJun 22, 2024
• Python

Import and export IP-XACT XML register models

• UpdatedOct 15, 2024
• Python

An IP-XACT DOM for IEEE 1685-2014 in Python.

• UpdatedMar 17, 2025
• Python

Contains examples to start with Kactus2.

• UpdatedAug 5, 2024
• Verilog

This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.

• UpdatedNov 17, 2024
• HTML

IP-XACT packaging of Pulpino by pulp-platform.org:https://github.com/pulp-platform/pulpino

• UpdatedDec 11, 2019
• Verilog

IP-XACT based CLI-tools

• UpdatedApr 12, 2017
• Mako

Library containing various VHDL IPs

• UpdatedJan 5, 2024
• SystemVerilog

Python-based IP-XACT parser

• UpdatedMar 27, 2017
• Python

A conversion tool for different IP-XACT versions.

• UpdatedNov 27, 2019
• XSLT

Various custom training projects related to Xilinx Zynq development.

• UpdatedNov 4, 2017
• HTML