hardware-description-language
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
Here are 164 public repositories matching this topic...
Language:All
Sort:Most stars
Haskell to VHDL/Verilog/SystemVerilog compiler
- Updated
Nov 5, 2025 - Haskell
Hardware Description Languages
- Updated
Jul 14, 2025
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
- Updated
Oct 25, 2025 - VHDL
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
- Updated
Sep 15, 2023 - Bluespec
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
- Updated
Jan 5, 2019 - VHDL
SystemRDL 2.0 language compiler front-end
- Updated
Nov 5, 2025 - C++
Fearless hardware design
- Updated
Aug 20, 2025 - Verilog
A core language for rule-based hardware design 🦑
- Updated
Oct 13, 2025 - Rocq Prover
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
- Updated
Oct 28, 2025 - Rocq Prover
Control and status register code generator toolchain
- Updated
Oct 10, 2025 - Python
ACT hardware description language and core tools.
- Updated
Nov 1, 2025 - C++
A new Hardware Design Language that keeps you in the driver's seat
- Updated
Nov 5, 2025 - Rust
Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone compute…
- Updated
Oct 2, 2020 - Python
A place to keep my synthesizable verilog examples.
- Updated
Apr 20, 2025 - Verilog
design and verification of asynchronous circuits
- Updated
Oct 4, 2025 - Python
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
- Updated
Dec 7, 2024 - Verilog
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
- Updated
Jun 6, 2024 - Verilog
🔁 elastic circuit toolchain
- Updated
Dec 2, 2024 - JavaScript
📚Repositório da Disciplina INE5406 - Sistemas Digitais
- Updated
Jun 21, 2018 - HTML
- Followers
- 491 followers
- Website
- github.com/topics/verilog
- Wikipedia
- Wikipedia