ghdl-yosys-plugin

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PyFPGA /HDLconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

vhdl verilog systemverilog ghdl yosys ghdl-yosys-plugin yosys-slang

UpdatedMar 5, 2025
Python

rodrigomelo9 /verifying-foss-hdl-synthesizers

Star12

a project to check the FOSS synthesizers against vendors EDA tools

vivado ise ghdl yosys iverilog verilator quartus pyfpga ghdl-yosys-plugin foss-synthesizers

UpdatedSep 26, 2020
Makefile

nobodywasishere /upduino-projects

Star7

Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

toolchain vhdl icestorm ghdl upduino upduino2 ghdl-yosys-plugin

UpdatedJan 8, 2023
VHDL

augustofg /ice40-ghdl

Star4

VHDL examples targeting the ICE40-HX8K development board using iceStorm + GHDL

fpga vhdl icestorm yosys ghdl-yosys-plugin

UpdatedJul 24, 2023
VHDL

PyFPGA /containers

Star2

Containers for FOSS tools

slang ghdl yosys ghdl-yosys-plugin verible surelog synlig vhd2vl sv2v yosys-slang

UpdatedJan 9, 2025
Shell

rafaelnp /fpga_dev_docker

Star2

Docker image for fpga development

docker fpga verification ghdl cocotb ghdl-yosys-plugin

UpdatedOct 5, 2021
Dockerfile

PyFPGA /symbiflow_cli

Star0

A possible replacement for openflow, which would be ideally contributed to the SymbiFlow project

icestorm ghdl yosys nextpnr prjtrellis ghdl-yosys-plugin

UpdatedAug 2, 2021
Python

JochiSt /icebreaker-VHDL

Star0

Some examples using VHDL in combination with the icebreaker board

simulation vhdl ghdl yosys icebreaker ghdl-yosys-plugin cxxrtl

UpdatedDec 10, 2024
Makefile

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