Cross-platform CLI and Python drivers for AIO liquid coolers and other devices

• UpdatedMar 5, 2025
• Python

**No Longer Maintained** Official RAMCloud repo

• UpdatedOct 16, 2019
• C++

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paperhttps://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

• UpdatedDec 11, 2024
• C++

DRAMSim2: A cycle accurate DRAM simulator

• UpdatedNov 11, 2020
• C++

MCMC toolbox for Matlab

• UpdatedAug 15, 2021
• MATLAB

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

• UpdatedSep 7, 2020
• Verilog

DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototypes are available on different FPGA boards. Described in our preprint:https://arxiv.org/pdf/2211.05838.pdf

• UpdatedSep 1, 2024
• VHDL

A 1MB chip RAM expansion for the A500+

• UpdatedJan 18, 2020

A High-Level DRAM Timing, Power and Area Exploration Tool

• UpdatedJul 29, 2020
• C++

Sample Arduino program to test 4164 DRAM chips.

• UpdatedMay 29, 2021
• C++

BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are used for DRAM on-die ECC but can be extended to apply to other linear block codes (e.g., BCH, Reed-Solomon). BEER is described in the 2020 MICRO paper by Patel et al.:https://arxiv.org/abs/2009.07985.

• UpdatedOct 9, 2020
• C++

A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.

• UpdatedMay 12, 2022
• C

Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used in our ISCA 2020 paper "Luo et al., CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off":https://people.inf.ethz.ch/omu…

• UpdatedSep 24, 2020
• AGS Script

FlippyRAM is an automated framework for testing and analyzing Rowhammer vulnerabilities in DRAM. It combines rowhammer tools and supports both Docker and ISO-based execution, making it a powerful resource for hardware security research.

• UpdatedJan 23, 2025
• C++

Bayesian Inference. Parallel implementations of DREAM, DE-MC and DRAM.

• UpdatedSep 8, 2020
• Python

DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-correction error characteristics using only the post-correction errors. Described in the 2019 DSN paper by Patel et al.:https://people.inf.ethz.ch/omutlu/pub/understanding-and-modeling-in-DRAM-ECC_dsn19.pdf.

• UpdatedDec 7, 2023
• C++

Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.

• UpdatedAug 8, 2019
• C

A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. This data and its analysis are described in the 2022 paper by Patel et al.:https://arxiv.org/abs/2204.10378

• UpdatedMay 4, 2022

This repository provides characterization data collected over 96 DDR3 SO-DIMMs, related to the following paper: Lee et al., "Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms", SIGMETRICS 2017.https://people.inf.ethz.ch/omutlu/pub/DIVA-low-latency-DRAM_sigmetrics17-paper.pdf

• UpdatedFeb 27, 2018
• AGS Script

Commodore C386SX-LT 2MB memory module schematics

• UpdatedApr 9, 2021