"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

• UpdatedJul 9, 2023
• Verilog

All my projects, homework, hand writings, course slides and anything I have learned and done during my studies at IUT😊. feel free to give it a ⭐=)

• UpdatedJan 18, 2025
• Jupyter Notebook

Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA

• UpdatedApr 23, 2023
• SystemVerilog

Final Project for Digital Systems Design Course, Fall 2020

• UpdatedJul 20, 2022
• Verilog

CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>

• UpdatedMar 13, 2024

Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications

• UpdatedDec 28, 2024
• Verilog

Implementation of a low-pass FIR filter in Verilog HDL.

• UpdatedApr 12, 2024
• Verilog

My activity in digital systems

• UpdatedApr 8, 2023

Implementation and verification of a hardware-based controller for a three-phase induction motor on an FPGA — Bachelor's Thesis [UPC-TTU, 2019]

• UpdatedApr 19, 2021
• VHDL

Digital Systems Design - Spring 2023 - Sharif University of Technology

• UpdatedApr 2, 2024
• Verilog

3-stage RISC-V Pipelined Processor with interrupt CSR support

• UpdatedJun 2, 2023
• SystemVerilog

Implementation of a FIFO structure for Digital Systems | Written in Verilog HDL

• UpdatedMar 26, 2024
• Verilog

Direct Digital Synthesizer for Generating Sine Waves using Verilog HDL

• UpdatedMar 29, 2024
• Verilog

Verilog implementation of the basic structure of an FPGA

• UpdatedMay 22, 2024
• Verilog

This GitHub repository Consists of materials, code samples, documentation, and valuable resources related to the Information Technology (IT) Department at the National Institute of Technology Karnataka (NITK). 📚 Resource Library 💻 Code Samples 🗂️ Project Repositories

• UpdatedJun 1, 2024
• Jupyter Notebook

Lab projects using Verilog HDL

• UpdatedApr 26, 2022
• Verilog

Repositorio con las 12 prácticas en VHDL para el curso impartido por la profesora Nayeli Vega, tomada en la ESCOM, IPN.

• UpdatedOct 17, 2021
• VHDL

FIFO Buffer Implemented in VHDL

• UpdatedOct 12, 2025
• VHDL

Digital Logic Design (DLD) is a fundamental subject for the engineering students worldwide. Well, many students find it difficult to design the digital circuits properly while pursuing the DLD course in colleges or universities. Therefore, I will try to assist those students by sharing my lab works with them.

• UpdatedDec 10, 2020

Binary Adder, Subtractor, Multiplier, Divider in VHDL with FPGA board.

• UpdatedApr 19, 2025
• VHDL