digital-logic-design

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

verilog vlsi 30daysofcode 30-days-of-code digital-logic-design verilog-programs digitalcircuit verilog-project rtl-design rtl-coding

UpdatedSep 30, 2023

fuad1502 /oombak

Star43

Oombak 🌊 is an interactive SystemVerilog simulator UI that runs on your terminal!

tui rtl verilog systemverilog digital-logic-design digital-logic-simulator ratatui

UpdatedOct 11, 2025
Rust

madhurimarawat /Semester-Notes

Star37

This repository includes academic notes, study materials, and resources from B.Tech (Hons) in CSE, specializing in Artificial Intelligence and Data Science. It features question papers, proprietary study guides, and resources to support learning in these fields.

data-visualization artificial-intelligence operating-system discrete-mathematics database-management entrepreneurship semester theory-of-computation object-oriented-programming computer-network study-materials probability-statistics digital-logic-design environmental-science professional-ethics engineeing-maths language-writing-skills computer-organization-architecture python-for-datascience semester-notes

UpdatedJun 26, 2025
HTML

raycar5 /logicsim

Star33

Composable digital logic simulation in Rust!

rust crates digital-logic-design digital-logic-simulator

UpdatedNov 30, 2020
Rust

shrine-maiden-heavy-industries /torii-hdl

Star29

A Python-based HDL and framework for silicon-based witchcraft

fpga hdl yosys digital-logic-design nextpnr asic-design torii-hdl

UpdatedNov 1, 2025
Python

Multimedia-Processing /Digital-Logic-Design

Star18

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

fpga digital vhdl verilog learn xilinx digital-logic systemverilog hdl verilog-hdl xilinx-fpga xilinx-vivado digital-logic-design altera-fpga altera-cyclone-v-sockit altera-cyclone-iii-de0 altera-quartus soc-kit altera-cyclone vhdl-verilog

UpdatedOct 25, 2023
Verilog

AryCra07 /TougHardware

Star12

BUPT 数字逻辑与数字系统课程设计项目

digital-logic-design vhdl-coursework

UpdatedJun 3, 2023
VHDL

Amey-Thakur /DIGITAL-LOGIC-DESIGN-AND-ANALYSIS-AND-DIGITAL-SYSTEM-LAB

Star10

CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>

computer-science engineering computer-engineering textbooks digital-systems digital-logic-design digital-system-design digital-systems-design digital-logic-design-lab ameythakur amey megasatish

UpdatedMar 13, 2024

SM2A /University_Projects

Star8

🎓💻All of my projects at University of Tehran

computer-graphics university-project cad artificial-intelligence operating-system computer-architecture compiler-design advanced-programming introduction-to-programming computer-networks digital-logic-design probability-and-statistics signal-system digital-logic-design-lab

UpdatedAug 11, 2024

harismuneer /Car-Parking-Controller

Star7

🚗 A Car Parking Simulator made in LogicWorks 5 as a final project for the course "Digital Logic Design (EE227)"

signals mux open-source-project car-park decoders clock-synchronization carpark carparking carparkingsystem dld digital-logic-design car-controller car-counter car-parking-simulator car-park-controller car-parking switch-programming parking-plaza

UpdatedJan 30, 2025

rohankalbag /vlsi-design

Star7

VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay

vhdl ngspice digital-logic-design brent-kung vlsi-design multiply-accumulate dadda-multiplier

UpdatedMay 10, 2023
VHDL

hasnainroopawalla /circuit-sim

Star7

Digital logic gate simulator using React, TypeScript and p5.js

react javascript typescript simulator webpack logic circuit-simulator p5js logic-gates logic-gate-simulator digital-logic-design

UpdatedNov 2, 2025
TypeScript

azizi-zahra /simple-vending-machine

Star6

DLD Project - A simple vending machine simulation with Verilog (Spring 2024)

verilog digital-logic-design

UpdatedJan 1, 2025
Verilog

ChaminduS /Building-a-RISC-V-CPU-Core

Star6

This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.

risc-v digital-logic-design cpu-design makerchip

UpdatedApr 25, 2021

ShashankVM /generic_systemverilog_designs_library

Star6

A library of useful, fully parameterized RTL designs implemented in SystemVerilog.

basic-learning systemverilog digital-logic-design

UpdatedMar 6, 2022
SystemVerilog

skamal16 /Mobile-Trainer-Board

Star6

My second semester project for my object-oriented programming course. A simulation game for the lab work done in my second semester Digital Logic Design course.

java simulator simulation object-oriented-programming digital-logic-design